Introduction : ‘Silicon LSIs (large-scale integrated circuit) have progressed remarkably in the past 25 years. In particular, complementary metal-oxide-semiconductor technology has plated a grate role in the progress of LSIs. By downsizing MOS field effect transistors (FETs), the number of transistors in a chip increases, and the functionality of the LSIs is improved, At the same time, the switching speed of MOSFETs citcuits increases and operation, speed of LSIs is improved. On the other hand system on chip technology has come in to widespread and as a result the LST system requires several functions such as logic, memory. analog functions. Moreover, the LS] system sometimes needs ultra-high speed logy or an ultra high-speed analog function,The MOS Transistor : The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor available is the “Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). These transistors are formed as a “sandwich” consisting of a semiconductor layer, usually a slice, or wafer, from a single crystal of silicon; a layer of silicon dioxide (the oxide) and a layer of metal. These layers are pattemed in a manner which permits transistors to be formed in the semiconductor material (the “substrate”); a diagram showing a typical (idealized) MOSFET is shown in Fig, 4.1.1, Silicon dioxide is a very good insulator, soa very thin layer, typically only a few hundred molecules thick, is required.Actually, the transistors which we will use do not use metal for their gate regions, but instead use polycrystalline silicon (poly). Polysilicon gate FET’s have replaced virtually all of the older devices using metal gates in large scale integrated circuits, (Both metal and polysilicon FET’s are sometimes referred to as IGFET’s --- insulated gate field effect transistors, since the silicon dioxide under the gate is an insulator. We will still continue to use the term MOSFET to refer to polysilicon gate FET’s.) The transistor consists of three regions, labeled the “source”, the “gate” and the “drain”, The area labeled as the gate region is actually a “sandwich” consisting of the underlying substrate material, which is a single crystal of semiconductor material (usually silicon); a thin insulating layer (usually silicon dioxide); and an upper metal layer. Electrical charge, or current, can flow from the source to the drain depending on the charge applied to the gate region.The semiconductor material in the source and drain region are “doped” with a different type of material than in the region under the gate, so an NPN or PNP type structure exists between the source and drain region of a MOSFET. Fig. 4.1.1 shows a cross section of both types of MOSFET. In Fig. 4.1.1(a), the source and drain regions are doped with N type material and the substrate doped with P type material. Such a transistor is called an N channel MOSFET. If they were doped with P type material, and the substrate doped with N type material as in Fig. 4.1.1(c) the device would be called a P channel MOSFET. The source and drain regions are quite similar, and are labeled depending on to what they are connected. The source is the terminal, or node, which acts as the source of charge carriers, charge carriers leave the source and travel to the drain. In the case of an N channel MOSFET, the source is the more negative of the terminals; in thecase of a P channel device, it is the more positive of the terminals. The area under the gate oxide is called the “channel” Source Gate Drain Vs OT RSs TT) (a) nMOS enhancement mode transistorSource Gate Drain (b) nMOS depletion mode transistorSource Gate Drain moun Pinon esos TTT) CT BRERE V. SON Sore errr eh ORIEN Lr ST ERTRRTI RN ON NO) PR XR RMR RR ON NRL SN ROM OOO NT SESSION, asa si “ Bes ORSON SS SS SS BORON NK NON CUCU OE SDS RNS SISK eh RS ROSSI SSIS SMS (c) PMOS enhancement mode transistorThe MOSFET can operate as a very efficient switch for current flowing between the source and drain region of the device. For the simplest type of MOSFET, the “enhancement mode MOSFET”, which acts as a “normally open” switch, the operation of the device can be described qualitatively with reference to Fig. 4.1.2 +Vos + Vos (a) (b) Fig. 4.1.2 : Enhancement mode nMOS operationFig. 4.1.2(a) shows an N-channel MOSFET with the source and drain connected to power (Vpp) and ground (Vss); the substrate, or body of the device, is also connected to ground. In this case, there is a reverse biased PN junction between at least one of the N wells and the substrate, so no current can flow through the substrate. In particular, there will be no current flow in the channel region under the gate of the transistor, and therefore no current will flow between the source and drain of the device. Under these conditions, the MOSFET is tuned off. Fig. 4.1.2(b) shows the same N-channel MOSFET with a positive charge applied to the gate of the device. Under these circumstances. if the gate is given a sufficiently large charge, negative charge carriers (clectrons) will be attracted from the bulk of the substrate material into the channel region immediately below the oxide under the gate. When more electrons are attracted into this region than there are positive charge carriers (holes) in the channel, then the channel effectively behaves as an N type region, and current can flow between the source and the drain. When this happens, the MOSFET is turned on.Note that a certain minimum charge must be appiied to the gate to overcome the excess of holes already in the channel region because of the P type doping in the substrate. This means that the switch is not turned on immediately; rather there must be some minimum amount of charge applied to the gate before the transistor is switched on. The voltage which must be applied to the gate before the transistor allows current to flow between the source and drain is called the “threshold voltage”, designated as VT,,. This type of transistor is called an N channel enhancement mode MOSFET. (It is called N channel because the conduction in the channel is due to N type charge carriers; it is said to be an “enhancement mode” device because the channel conduction is enhanced by a charge applied to the gate.) Fig. 4.1.4 shows a set of typical characteristic curves for the current Ips between the drain and source of a MOSFET as a function of the voltage Vijg for a range of gate voltages, Vosal (a) Fig. 4.1.3: (b) Depletion mode nMOS operationA second type of MOSFET can also be constructed; this type of device is commonly used in purely NMOS designs, but is not used in CMOS designs (Presently, we only have access to CMOS processes.) This type of MOSFET, the “depletion mode MOSFET”, acts as a “normally closed” switch. Its behavior can qualitatively be explained with reference to Fig. 4.1.4 which shows an N channel depletion mode MOSFET. 7 'p Vest VGs: Ves3. Vos Fig. 4.1.4 : Characteristics of MOSFETIn the depletion mode MOSFET, a thin layer of semiconductor material immediately beneath the gate oxide is permanently doped with the same ‘type material as the source and drain regions (but different from the bulk of the substrate semiconductor material). This thin layer allows conduction to occur in the channel region when no charge is applied to the gate. If a negative charge is applicd to the gate, then the negative charge carriers in the thin N-doped region immediately beneath the gate oxide will be repelled from this region, leaving no free charge carriers, and conduction will cease. In the depletion mode MOSFET, a charge (with the same polarity as the drain dopant) applied to the gate turns the transistor off. Depletion mode MOSFETs find their most common use not as switches but as tesistors. As a permanently “on” transistor, the device has a high resistance compared with the doped semiconductor material itself, and the resistance is readily variable by modifying the size of the transistor. (At fabrication time, the resistance can be modified by varying the number of ions which are implanted in the gate region of the device).Both enhancement and depletion mode transistors are used in many of today’s microelectronic circuits, The most popular circuit technology using both enhancement and depletion mode devices is the conventional NMOS technology. In this technology, depletion mode transistors are mainly as resistors and enhancement mode transistors are used as switches.Physical Structure of the MOSFET : In this section, a description of a structure of a MOSFET in order to delinate the physical and geometrical regions of the device and to define electrodes and terminals. The n-type inversion channel silicon MOSFET is shown in Fig. 4.2.1 V5 @ Source Vv. Oe Drain x n-type inversion Kw substrate channel ‘Substrate body Gate oxide1) Co-ordinate System : The most common geometry used in VLSI chips is rectangular co-ordinate system as shown in Fig. 4.2.1 i) The x-axis denotes the depth direction into the silicon substrate ii) The y-axis denotes the channel length direction along which the current flows known also as the longitudinal direction since it is longitudinal to current flow. iii) Thus, the x-direction in the oxide film is the direction of the transverse electric field that controls the current i.e. the oxide field (x-direction) is transverse to the current (y-direction) iv) The z-axis denotes the width direction both for the gate width and the channel width. 2) Body of the Semiconductor : i) The semiconductor body of the n-channel MOSFET is the p-type substrate. It is also known as bulk or base ii) The d.c. voltage applied to the wire connected to the body electrode is denoted by V, (from x-axis)3) ii) iii) iv) 4) ii) Source and Drain : The two n+ regions form the two n+ / p junctions, The ‘+’ sign means the n- type region is heavily doped and has very high conductivity. nt source region is the source of the charge carriers that flow in the channel. The n-type drain region is the sink or drain of the charge carriers. ‘The source and drain junction areas are different and the adjacent gate oxides contain different densities of oxide and interface trap created by the different high electric fields near the source and drain junctions. Gate oxide, Gate contact, Gate width : The third region of the MOSFET is the surface oxide layer between the source and drain. This layer is thin, pure, defect free and 50-2000 A° thick thermally grown oxide. It serves as the dielectric layer so that the gate can sustain as high as I x 10° to 5 x 10° V/cm transverse electric field in order to strongly modulate the conductance of the channel. This is known as Gate oxide. Above the gate oxide is a thin gate electrode layer made of metal which can be aluminium, a highly doped silicon.iii) 5) iii) The geometrical width of the gate conductor electrode Z :s called pats x. Symbol W is often used for gate width instead of Z. Channel type, Channel length and Channel thickness : Below the gate oxide is a thin n-type inversion layer on the surface of the p- type substrate. It is induced by the oxide electric field from the applied gate voltage V,. This is known as inversion channel. It is the conduction chains! that allows, the electrons to flow from source to the drain. The geometrical channel length is labeled by ‘L’. The electrical channel is shorter than geometrical channel The clectrical channel thickness is labeled by X.. In doped n-channel MOSFET, this is equal to the geometrical thickness of the doped channe! or the depth of the n/p+ junction of the doped layer minus the thickness of the junction space-charge layer on the doped n-channel side6) Field oxide, Pad oxide : The oxide layers under the source and drain contact bonding pads about 5000°A, this reduces the loading capacitance and increases the diclectric breakdown voltage to allow the drain to be biased to higher voltages. The oxide at the two width edges (Z-direction) of the gate is also thicker. These thick oxides, surrounding the thin gate oxide and covering the drain and source junctions are known as the field oxides and those under the wire bonding metal pad are known as pad oxides.MOS Structure : The metal oxide semiconductor (MOS) structure is shown in Fig. 4.4.1. The structure consist of three layers, semiconductor substrate (generally P type), insulating layer of silicon oxide (SiO,) and metal gate of aluminium (now a days polysilicon is used instead of aluminium) Al SiO. Ohmic contactThis structure is also known as MOS capacitor with metal plate and semiconductor plate and oxide as an dielectric. The energy band diagram of an ideal P-type semiconductor MOS at V = 0 is shown in Fig. 4.4.1. 1) The work function is the energy difference between the Fermi level and the vaccum level (i.e. q >, for metal and q , for the semiconductor) 2) Also shown are the electron affinity qx which is the energy difference between the conduction band edge and the vaccum level in the semiconductor. 3) q bpp, which is the energy difference between the Fermi level E,, and the intrinsic level E,Vaccum level E,, (Freespace) £, (Conduction Band) E; (Intrinsic fermi level) E, (Fermi level) VATA, Walence Band) Semiconductor oxide Fig. 4.4.2 : Energy band diagram of ideal MOS structure at V = 0An ideal MOS is defined as, at zero applied bias, the energy difference between the metal work function q $,, and the semiconductor work function q hors zero or the work function differene q ,,. is zero. E 4 Gus = 44,794) =46,-| 145 +4 4| =0 For p-type substrate as = Om [xB aby] <0 For n-type substrate whereE, - Energy bandgap $,, ~ Metal work function in eV x - Electron affinity orp ~ Energy difference between E, and E, for p-type 44, ~ Energy difference between E,, and E, for n-type In other words, (1) The energy band is flat (Flat band condition) when there is no applied voltage (2) The only charges that exist in the diode under any biasing conditions are thos: in the semiconductor and those with equal but opposite sign on the meta surface adjacent to the oxide.There is no carrier transprrt through the oxide under direct current biasing (3) conditions or resistivity of the oxide is infinite. The above condition is also known as flat band condition where t “n, byp= gm NU | (N, >> n) and by,= Sin () (N, >> n) Where. N,, = Donor ion concentration N, = Acceptor ion concentrationIn the semiconductor, the bottom of the conduction band E.. 1s located at a fixed energy separation from E,. This energy difference between E, and E, in the semiconductor is labeled as electron affinity and denoted by greck letter x (chi). The affinity is therefore the energy needed to move an electron from the bottom of the conduction band and place it at rest outside the solid. This work function can be Tepresented as qd, = HTL E.-E, |E Metal (Al) c Oxide (SiO, ) - __ Semiconductor (Si) 4, ; | G7 0.95 eV | 06 | %, | | le =11eV Band gap energy g | E,=8eV ne Ha i | \ | ee 9 i FP 7 Fig, 4.4.3 : Energy band diagram for components of MOS structure1) The substrate has a bandgap of about 1.1 eV (for silicon) and electron affinity of about 4.15 eV. 2) The insulating silicon dioxide between silicon and metal gate has large bandgap of about 8 eV and electron affinity of 0.95 V. 3) The work function of a metal (A1) is about 4.1 eV. The flat band voltage Vrp is obtained when the applied gate voltage cquals the work function difference between the gate metal and the semiconductor. If there is also a fixed charge in the oxide and or at the oxide-silicon interface, the expression for the flat band voltage must be modified accordingly. Flat band voltage can be given asVen = bm-, Volts or Veg = on. a ox Built in potential V,; can be as Vii = Weep =9 bm — 4, Volts $,>,, or V,,<0 for p-type silicon b,<$, or V,,>0 — for n-type silicon9, = Surface potential Fig, 4.4.4 : Energy band diagram for MOS structure showing the band bendingBiasing of MOS Structure : When the MOS structure is biased with positive or negative voltages at the gate and the substrate, the energy band diagram changes. The electrical behaviour of the MOS structure under external bias is discussed in this section. In this case the substrate voltage V,, is assumed to be zero. Then three different cases arise. In the following each case is explained in detail.1) Accumulation Region : The situation for large negative bias on the gate w.r.t. the substrate is depicted in the Fig. 4.5.1. 1) The large negative charge on the metal plate is balanced by holes attracted to the silicon-silicon dioxide (Si-SiO.) interface directly below the gate. 2) For the bias condition shown the hole density at the. surface exceeds that which is present in the original P-type substrate and the surface is said to be operating in the accumulation region or just in accumulation. 3) This accumulation layer is extremely shallow, existing primarily as a charge sheet directly below the gate. 4) The oxide electric field is directed towards the gate. So the negative surface potential causes the energy bands to bend upward near the surface 5) Since the majority carriers are attracted towards the gate the minority carriers (clectrons) are pushed into the substrate because of negative voltage. 6) The valance band bends upwards and is closer to the fermi level and the fermi levels remain constant through the MOS structure.Metal Fm oxide Hole accumulation substrate teettettes metal Semiconductor Fig, 4.5.1; Accumulation in MOS structure2) Depletion Region : A small positive voltage is applied to the gate, then 1) 2) 5) The holes are repelled from the surface. Eventually. the hole density near the surface is reduced below the majerity carrier level set by the substrate doping level as shown in Fig. 4.5.2. This condition is called as depletion and region is called depletion region The region beneath the metal clectrode is depleted of free carriers in much the same way as the depletion region that exists near the metallurgical junction of the pn junction diode In the Fig. 4.5.2, positive charge on the gate clectrode is balanced by the negative charge of the ionized acceptor atoms in the depletion layer, The depletion region width X, can range from a fraction of a micron to many tens of microns depending on the applicd voltage and substrate doping levelsV2 0 (Small) Metal P-type substrate | \_ Depletion GND region Fig, 4.5.2 : Depletion in MOS structureMobile hole charge density in thin layer parallel to silicon surface can be represented as, dQ =-qN,dx Change in the surface potential to displace dQ (Poisson equation) can be given as d= -2aQ si . Na =x dxBy solving above equation WN, 2 QQ = Ze, _ Ped @i xy aN, ol) 6) — Depletion region charge density is given by Q = - WN, Q = ~Y2ONy esl Q-QI -Q)3) 2) 3) 4) Inversion Region : As the voltage of the gate electrode increases further then The electrons are attracted to the surface and the electron density at the surface will exceed the hole density. At this voltage, the surface has inverted polarity from the p-type of the: original substrate to an n-type inversion layer, directly underneath the top plate. This inversion region is an extremely shallow layer existing primarily as a charge sheet directly below the gate. The high density of electrons in the inversion layer is supplied by the electron — hole generation process within the depletion layer. The positive charge on the gate is balanced by the combination of negative charge in the inversion layer plus negative ionic acceptor charge in the depletion layer.5) — The voltage at which the surface inversion layer. forms plays an extremely important role in MOSFET and is called the threshold voltage V,,,,. by putting the inversion condition in Equation (2) we get the inversion region depth Xam aS _ [212 op | (Q,=~ op) ~ aNa The depletion charge density at surface inversion Q,,,can be given as ‘dm Xam = Xq Qo = Dean =-qNa Xan -\ 2qN, €y! 2 op |V> 0 (large) Metal oxide inversion region 7 ~cywene | en ie | P-type substrate a Metal (al) | oxide | Semiconductor (Si) GND Fig, 4.5.3 : Inversion in the MOS structure