Вы находитесь на странице: 1из 22

CHAPTER 2

C2XX DSP CPU AND


INSTRUCTION SET
By:
Dr. Dheeraj Joshi
Associate Professor
Introduction
C2xx DSP core is heart of the LF2407 DSP Controller
Core is a 16-bit fixed point processor
C2xx core has its own native instruction set of assembly mnemonics or commands
Provides freedom of writing code in both C language and assembly language
best to compose code in assembly language
Components of the C2xx DSP Core

Consists of several subcomponents necessary to perform arithmetic operations


A 32-bit central arithmetic logic unit (CALU)
A 32-bit accumulator (used frequently in programs)
Input and output data-scaling shifters for the CALU
A (16-bit by 16-bit) multiplier
A product-scaling shifter
Eight auxiliary registers (AR0 AR7) and an auxiliary register arithmetic unit
(ARAU)
Central Arithmetic Logic Unit
(CALU)
C2xx performs 2s-complement arithmetic using the 32-bit CALU
CALU uses 16-bit words taken from data memory
Derives data from an immediate instruction, or from the 32-bit multiplier result
CALU can perform Boolean operations
CALU provides better transparency because it is not accessed directly by user
Accumulator
Stores the output from the CALU
Also serves as another input to the CALU
Accumulator is 32 bits wide, divided into two sections, each consisting of 16 bits (high-
order bit from 16 31, low-order bit from 0 15)
Written to and read from directly by the user code via assembly commands
It also provide better transparency
Scaling Shifters
C2xx has three 32-bit shifters that allow for scaling, bit extraction, extended arithmetic,
and overflow-prevention operations
Facilitates shifting data left or right
Any one of the three shifters could be used depending on the specific instruction entered
1. Input data-scaling shifter (input shifter): Left-shifts 16-bit input data by 0 to 16 bits to
align the data to the 32-bit input of the CALU
2. Output data-scaling shifter (output shifter): Left-shifts data from the accumulator by
0 to 7 bits before the output is stored to data memory. The content of the accumulator
remains unchanged
3. Product-scaling shifter (product shifter): PREG receives the output of the multiplier.
Shifts the output of the PREG before that output is sent to the input of the CALU. Has
four product shift modes (no shift, left shift by one bit, left shift by four bits, and right
shift by six bits). Useful for performing multiply/accumulate operations, fractional
arithmetic, or justifying fractional products
Multiplier
Performs 16-bit, 2s-complement multiplication and creates a 32bit result
For multiplexing, C2xx uses the 16-bit temporary register (TREG) and the 32-bit product
register (PREG)
Multiplexing operation is not as transparent as CALU or Shifters
TREG is loaded with one of the numbers to be multiplied
Output of the multiply is stored in the PREG
Auxiliary Register Arithmetic Unit
(ARAU) and Auxiliary Registers
generates data memory addresses when an instruction uses indirect addressing to access
data memory
Eight auxiliary registers (AR0 through AR7) support ARAU, each can be loaded with a
16-bit value from data memory or directly from an instruction
Each auxiliary register value can also be stored in data memory
Auxiliary registers mainly used as pointers to data memory locations, facilitating
looping or repeating algorithms
automatically incremented or decremented by particular assembly instructions
Auxiliary register pointer (ARP) embedded in status register ST0 references the auxiliary
register
status registers (ST0, ST1) are core level registers where values such as the Data Page
(DP) and ARP located
Mapping External Devices to the C2xx
Core and the Peripheral Interface
Peripherals are mapped to data memory
Each peripheral is mapped to a corresponding block of data memory addresses
Each corresponding block contains configuration registers, input registers, output
registers, and status registers
Each peripheral is accessed by simply writing to the appropriate registers in data memory
(provided the peripheral clock is enabled)
peripherals are linked to the internal memory interface of the CPU through the PBUS
interface
All on-chip peripherals are accessed through the Peripheral Bus (PBUS)
All peripherals, excluding the WD timer counter, are clocked by the CPU clock
Functional block diagram of the LF2407 DSP
controller
System Configuration
Registers
System Control and Status Registers (SCSR1, SCSR2), used to configure or display
fundamental settings
these fundamental settings include the clock speed (clock pre-scale setting)
Bits are controlled by writing to the corresponding data memory address or the
logic level on an external pin
System Control and Status Register 1
(SCSR1) Address 07018h

R = read access, W = write access, C = clear, -0 = value after reset


Bit 1, 8, 15 Reserved
Bit 14 CLKSRC. CLKOUT pin source select
0 CLKOUT pin has CPU Clock (40 MHz) as the output
1 CLKOUT pin has Watchdog clock as the output
Bit 13 LPM (1:0). Low-power mode select. Indicate which low-power mode is
entered when the CPU executes the IDLE instruction
Bits 119 PLL Clock prescale select. Selects PLL multiplication factor for I/P clock

Note: In order to modify/read the register contents of any peripheral, the clock to that
peripheral must be enabled by writing a 1 to the appropriate bit
Bit 7 ADC CLKEN. ADC module clock enable control bit
Bit 6 SCI CLKEN. SCI module clock enable control bit
Bit 5 SPI CLKEN. SPI module clock enable control bit
Bit 4 CAN CLKEN. CAN module clock enable control bit
Bit 3 EVB CLKEN. EVB module clock enable control bit
Bit 2 EVA CLKEN. EVA module clock enable control bit
For Bit 2 7:
0 Clock to module is disabled
1 Clock to module is enabled and running normally
Bit 0 ILLADR. Illegal Address detect bit
If illegal address occurs, this bit will be set.
Cleared by writing a 1 to it and should be cleared as part of the initialization
sequence.
Note: An illegal address will cause a Non-Maskable Interrupt (NMI).
System Control and Status Register 2
(SCSR2) Address 07019h

R = read access, W = write access, C = clear, -0 = value after reset


Bit 15 7 Reserved
Bit 6 Input Qualifier Clocks
qualifies the input signal to the CAP16, XINT1/2, ADCSOC, and PDPINTA/B pins in the 240xA devices
Not used by I/O functions of these pins
state of the internal input signal will change only after the pin is held high/low for 6 (or 12) clock edges
internal clock is not the same as CLKOUT, although its frequency is the same as CLKOUT
0 The input-qualifier circuitry blocks glitches up to 5 clock cycles long
1 The input-qualifier circuitry blocks glitches up to 11 clock cycles long Note
Bit 5 Watchdog Override. After RESET, disables the WD function through software
(by setting the WDDIS bit = 1 in the WDCR). This bit is a clear-only bit and defaults to a
1 after reset. Cleared by writing a 1 to it
0 Protects WD from being disabled by software. Cannot be set to 1 by software.
1 Default reset value and allows the user to disable the WD through the WDDIS bit in
the WDCR. Protects the integrity of the WD timer
Bit 4 XMIF Hi-Z Control. controls state of external memory interface
0 XMIF signals in normal driven mode; i.e., not Hi-Z (high impedance)
1 All XMIF signals are forced to Hi-Z state
Bit 3 Boot Enable. reflects state of BOOT_EN / XF pin at reset
0 Enable Boot ROM
1 Disable Boot ROM
Bit 2 Microprocessor/Microcontroller Select. Reflects state of MP/MC pin at
reset
0 Set to Microcontroller mode, 7FFF is mapped internally (i.e., Flash)
1 Set to Microprocessor mode, 7FFF is mapped externally (i.e., External memory device.)
Bit 1 0 SARAM Program/Data Space Select
Memory
2 ways of using the physical memory on board storing a program, storing data
program to be run must be stored in memory that is mapped to program space
memory that is in data space may be used to store data
Data memory written to during the execution of a program
Data memory used as temporary storage
Memory blocks B1 and B2 are configured as data memory
B0 block intended to hold data, but can be configured to act as either program or data
memory, depending on the value of the CNF bit in Status Register ST1
CNF = 0 maps B0 in data memory, CNF = 1 maps B0 in program memory
memory addresses associated with SARAM can be configured for both data memory and
program memory
When configured for internal, SARAM used as data/program memory. When configured as
external, used for off-chip program memory
In the case of the Spectrum Digital EVM, external memory is installed on the board and a
jumper pulls the MP/MC pin high or low.
Memory
Maps
Code resides in
and is run from
program memory
space
program memory
can also store
immediate
operands and
table information
This figure is
program memory
map for LF2407
These factors determine configuration of program memory:
CNF Bit: Determines if B0 memory is in on-chip program space
CNF = 0 The 256 words are mapped as external memory.
CNF = 1 The 256 words of DARAM B0 are configured for program use.
At reset, B0 is mapped to data space (CNF = 0)
MP/MC pin: The level on the MP/MC pin determines if program instructions are read from
on-chip Flash/ROM or external memory
MP/MC = 0 Configured in microcontroller mode. The on-chip flash EEPROM is
accessible. The device fetches the reset vector from on-chip memory.
MP/MC = 1 The device is configured in microprocessor mode. Program memory
is mapped to external memory.
Q/A