Princess Sumaya University 4241 Digital Logic Design Computer Engineering

Dept.
Registers
Group of D Flip-Flops I0 D Q A0

Synchronized (Single Clock) R

Store Data I1 D Q A1

I2 D Q A2

I3 D Q A3
CLK
R
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Reset
 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Registers
I0 D Q A0
CLK
I3 R
I2 I1 D Q A1
I1
R
I0
A3 I2 D Q A2
A2 R
A1
I3 D Q A3
A0
CLK
Note:
Note New data has to go in R
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with every clock Reset
 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Registers with Parallel Load
Control Loading the Register with New Data

D7 Q7
D6 R Q6
E Q5
D5 LD Q(t+1)
G
D4 I Q4 0 Q(t)
D3 S Q3 1 D
D2 T Q2
E
D1 Q1
R
D0 Q0
LD

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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Registers with Parallel Load
Should we block the Clock to keep the Data?

D7 Q7
R I0 D Q A0
D6 Q6
E Q5
D5
G
D4 Q4 I1 D Q A1
I
D3 S Q3
D2 T Q2 I2 D Q A2
E Delays
D1 Q1
R the
D0 Q0 Clock
LD I3 D Q A3
Load
CLK
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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Registers with Parallel Load
Circulate the old data

I0 MUX
Y D Q A0
I0 I1 S

I0 MUX
I1
Y D Q A1
I1 S

I0 MUX
Y D Q A2
I2 I1 S

I0 MUX
I3
Y D Q A3
I1 S
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Load CLK
 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Shift Registers
4-Bit Shift Register

Serial SI SO
Input D Q D Q D Q D Q
Serial
Output

CLK

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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Shift Registers
Q3 Q2 Q1 Q0
SI D Q D Q D Q D Q SO

CLK

CLK
SI
Q3
Q2
Q1
Q0 7 / 28
 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Serial Transfer

SI SO SI
Shift Register A Shift Register B

Clock CLK CLK

Shift
Control
Clock

Shift
Control
CLK

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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Serial Addition

Shift SI
Control Shift Register A
x
S
y FA
z C
CLK Shift Register B

Q D

CLR
Clear

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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Universal Shift Register
Parallel-in Parallel-out
Serial-in Serial-out
Serial-in Parallel-out
Parallel-in Serial-out

D Q D Q D Q D Q

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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Universal Shift Register

Q3 Q2 Q1 Q0

Q Q Q Q

CLR
D D D D
CLK
S1 S1 Y
S0 S0 MUX
I3 I2 I1 I0

SI SI
for for
SR SL
D3 D2 D1 D0
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Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Universal Shift Register

S1 Q3 Q2 Q1 Q0 CLR
S0 USR
SRin D3 D2 D1 D0 SLin

Mode Control
Register
S1 S0 Operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Ripple Counters
Ripple Asynchronous
Q3 Q2 Q1 Q0

Q T 1 Q T 1 Q T 1 Q T 1
CLK
CLR CLR CLR CLR
CLR
CLK
Q0
Q1
Q2
Q3 13 / 28
 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Ripple Counters
Q3 Q2 Q1 Q0

Q D Q D Q D Q D
CLK
Q Q Q Q

CLK
Q0
Q1
Q2
Q3
0 1 2 3 4 5 6 7 8 9 14 / 28
 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
BCD Ripple Counter

0000 0001 0010 0011 0100

1001 1000 0111 0110 0101

Q3 Q2 Q1 Q0

Q J Q J 1 Q J Q J 1
CLK
Q K 1 Q K 1 Q K 1 Q K 1

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Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Decades Counter

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

BCD BCD BCD

Count
Counter Counter Counter
(CLK)

100s Digit 10s Digit 1s Digit

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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Synchronous Binary Counter

Q3 Q2 Q1 Q0
Enable

Q J Q J Q J Q J

Q K Q K Q K Q K
To CLK
Next
Stage

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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Up-Down Binary Counter

Q3 Q2 Q1 Q0

Q T Q T Q T Q T

Q Q Q Q
CLK

Up

Down

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Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
BCD Counter
0 0 0 0 0

1 1 1 1
0000 0001 0010 0011 0100
1 1
1001 1000 0111 0110 0101
1 1 1 1

0 0 0 0 0

Q3 Q2 Q1 Q0
E

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Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
BCD Counter
0 0 0 0 0

1 1 1 1
0000 / 0 0001 / 0 0010 / 0 0011 / 0 0100 / 0
1 1
1001 / 1 1000 / 0 0111 / 0 0110 / 0 0101 / 0
1 1 1 1

0 0 0 0 0

Q3 Q2 Q1 Q0
y E

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Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Binary Counter with Parallel Load

I3 Q3
CLR LD Count Q(t+1)
I2 Q2
0 x x 0
I1 Q1
1 0 0 Q(t)
I0 Q0
1 0 1 Q(t)+1
LD
1 1 x I
Count
CLR

Usually Asynchronous Clear

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Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
BCD Counter Example

LD
0 I3 Q3 A3
0 I2 Q2 A2
0 I1 Q1 A1
0 I0 Q0 A0
Count Count
CLR

1 CLK
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Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Ring Counter

0001 0010 0100 1000

T3 T2 T1 T0 CLK
T0
2-to-4 Decoder T1
T2
2-bit counter T3

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Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Johnson Counter

0000 0001 0011 0111

1000 1100 1110 1111

Q3 Q2 Q1 Q0

Q D Q D Q D Q D

Q Q Q Q
CLK
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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Homework
Mano
Chapter 6
6-2
6-3
6-4
6-13
6-14
6-16
6-18

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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Homework
6-2 Include a synchronous clear input to the Register with
Parallel Load. The modified register will have a parallel
load capability and a synchronous clear capability. The
register is cleared synchronously when the clock goes
through a positive transition and the clear input is equal
to 1.

6-3 What is the difference between serial and parallel

transfer? Explain how to convert serial data to parallel
and parallel data to serial. What type of register is
needed?

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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Homework
6-4 The content of a 4-bit register is initially 1101. The
register is shifted six times to the right with the serial
input being 101101. What is the content of the register
after each shift?
6-13 Show that a BCD ripple counter can be constructed using
a 4-bit binary ripple counter with asynchronous clear and
a NAND gate that detects the occurrence of count 1010.

6-14 How many flip-flop will be complemented in a 10-bit

binary ripple counter to reach the next count after the
following count:
(a) 1001100111
(b) 0011111111
(c) 1111111111
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 Princess Sumaya University 4241 Digital Logic Design Computer Engineering
Dept.
Homework
6-16 The BCD ripple counter has four flip-flops and 16 states,
of which only 10 are used. Analyze the circuit and
determine the next state for each of the other six unused
states. What will happen if a noise signal sends the circuit
to one of the unused states?

6-18 What operation is performed in the up-down counter

when both the up and down inputs are enabled? Modify
the circuit so that when both inputs are equal to 1, the
counter does not change state, but remains in the same
count.

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