Traditional (CISC) Machines

Complex Instruction Set Computers (CISC)

complicated instruction set

different instruction formats and lengths
many different addressing modes
e.g. VAX or PDP-11 from DEC
e.g. Intel x86 family

Reduced Instruction Set Computer (RISC)

 Traditional (CISC) Machines

Complex Instruction Set Computers (CISC)

Generally a large and complicated instruction
set
Implementation of such architecture in
hardware tends to be complex
 VAX Architecture
It was introduced by DEC( Digital Equipment corporation) in
1978
Share the same machine in a multi user environment
Memory ( 8 bit bytes )
All addresses are byte address
word (2bytes), longword (4bytes),
quadworad (8bytes), octaword (16bytes)
All VAX programs operate in a virtual address space of 232
bytes ( to access large extremely large memory)
One half is used for system space (contains OS shared
by all programs)
The other half is called process space, and is defined
separately for each program
 VAX Architecture

Registers
16 general purpose registers: R0~R15
each register is 32-bit long
R15 (PC): Program Counter
R14 (SP): Stack Pointer ( use other register)
R13 (FP): Frame Pointer ( build a DS called Stack and places
its address in FP
R12 (AP): Argument Pointer (used to pass list of arguments)
R6~R11: general
R0~R5: are used by some instructions
PSL: process status longword contains variable and
flags associated with in a process
 VAX Architecture

Data Formats
Integers: byte, word, longword, quadword, or octaword
Negative integers: 2s complement representation
Floating-point: 4~16bytes
packed decimal: (C:positive, D:negative, F:unsigned)

4 4 4 4 4 S
zoned decimal: (digits are represented with ASCII codes)

0011 4 0011 4 S 4
e.g. +53842, 53842C (packed), 35333834C2 (zoned)
e.g. -6071, 6071D(packed), 363037D1
numeric format: trailing numeric, leading separate
numeric
 VAX Architecture

Instruction Formats
variable -length instruction format
Addressing Modes
register mode operand itself may be in the register
register deferred mode -address may be specified by the reg
Auto increment and auto decrement modes
register content may be increment or decrement
several base relative addressing modes displacement field
program-counter relative modes
indirect addressing mode (called deferred modes)
immediate operands
 VAX Architecture
Instruction Set
Goal: symmetric with respect to data type
The instruction mnemonics are formed by
a prefix that specifies the type of operation
a suffix that specifies the data type of the operands
a modifier that gives the number of operands involved
e.g. ADDW2, MULL3, CVTWL(conversion from word to long
word)
A single instruction for
saves a designated set of registers
passes a list of arguments to the procedure
maintains the stack, frame, and argument pointers
sets a mask to enable error traps for arithmetic operations
 VAX Architecture

Input and Output

I/O device controllers
Each controller has a set of control/status and data
registers, which are assigned locations in the
physical address space (called I/O space)
No special instructions are required to access
registers in I/O space
The association of an address in I/O space with a
physical register in a device controller is handled by
the memory management routines
 Pentium Pro Architecture
Memory
physical level: 8 bit bytes byte addresses,
two consecutive byes form a word
four bytes form a doubleword
logical level: segments and offsets
Segment may be in different size and different purpose
some for execution and some for storing
In some cases, a segment can also be divided into pages
Some pages may be in physical memory and some
stored on disk
The segment/offset address specified by the programmer
is translated into a physical address by the x86 MMU
(Memory Management Unit)
 Pentium Pro Architecture
Registers
General-purpose registers:
EAX, EBX, ECX, EDX: data manipulation
ESI, EDI, EBP, ESP: address
Special-purpose registers:
EIP: next instruction (32 bit register) points next instrn
FLAGS: status word (32 bit register)

CS: code segment register address of current executable code

SS: stack segment register address of16-bit
the segment registers
current stack segment
DS, ES, FS, and GS: - used to indicate the address of data
segments
Floating-point unit (FPU)
Registers reserved for system programs
 Pentium Pro Architecture
Data Formats
Integers:
8-, 16-, 32-bit binary numbers
negative values: 2s complement
FPU can also handle 64-bit signed integers
The least significant part of a numeric value is stored at the
lowest-numbered address (little-endian)
binary coded decimal (BCD)
unpacked: 0000____0000____0000____...0000____
packed: |____|____|____|____|____|____|..|____|____|
Floating-point data formats
single-precision: 32 bits=24+7-bit exponent+sign bit
double-precision: 64 bits=53+10-bit exponent+sign bit
extended-precision: 80 bits=64+15-bit exponent+sign bit
 Pentium Pro Architecture
Instruction Formats
prefix (optional) containing flags that modify the operation
of instruction
specify repetition count, segment register, etc.
opcode (1 or 2 bytes)
operands and addressing modes
Addressing Modes
TA=(base register)+(index register)*(scale factor)+displacement
base register: any general-purpose registers
index register: any general-purpose registers except ESP
scale factor: 1, 2, 4, 8
displacement: 8-, 16-, 32- bit value
eight addressing modes
 Pentium Pro Architecture
Instruction Set
400 different machine instructions
R-to-R instructions, R-to-M instructions, M-to-M instructions
immediate values,
special purpose instructions for high-level programming
language
entering and leaving procedures,
checking subscript values against the bounds of an array
Input and Output
Input is performed by instructions that transfer one byte,
word, or doubleword from an I/O register EAX
Repetition prefixes allow these instructions to transfer an
entire string in a single operation
 Questions

What is the difference between the

instructions LDA # 3 and LDA THREE?
In the first instruction immediate addressing is
used. Here the value 3 is directly loaded into
the accumulator register.
In the second instruction the memory
reference is used. Here the address (address
assigned for the symbol THREE) is loaded into
the accumulator register
 Differentiate trailing numeric and leading separate numeric.
The numeric format is used to represent numeric values with one digit
per byte. In the numeric format if the sign appears in the last byte it is
known as the trailing numeric. If the sign appears in a separate byte
preceding the first digit then it is called as leading separate numeric

What are the addressing modes used in VAX architecture?

Register direct, register deferred, auto increment and decrement,
program counter relative, baserelative, index register mode and indirect
addressing are the various addressing modes in VAXarchitecture.

How do you calculate the actual address in the case of register

indirect with immediate index mode?
Here the target address is calculated using the formula
T.A =(register) + displacement.
 What is the use of TD instruction in SIC
architecture?
The test device (TD) instruction tests whether the
addressed device is ready to send or receive a byte
of data.The condition code is set to indicate the result
of this test. Setting of < means the device is ready to
send or receive, and = means the device is not ready.

Write the sequence of instructions to perform

the operation BETA = ALPHA+5 using SIC/XE
instructions.