8086 Microprocessor

It is a 16 bit p.
8086 has a 20-bit address bus can access
up to 220 memory locations(1 MB)
It can support up to 64K I/O ports.
It provides 14, 16-bit registers.
It has multiplexed address and data bus
AD0- AD15 and A16 A19.
 It requires +5V power supply.
A 40 pin dual in line package.
It can pre fetches up to 6 instruction bytes
from memory and queues them in order to
speed up instruction execution.
8086 is designed to operate in two modes,
Minimum and Maximum.
 Arithmetic Logic Unit (ALU)
Addition OPERAND A
Subtraction
Multiplication
RESULT
Division
Comparison
Logic Operations

OPERAND B

CONTROL
 Arithmetic Logic Unit (ALU)
A B F Y
n bits n bits
0 0 0 A+ B
0 0 1 A -B
Carry
0 1 0 A -1
Y= 0 ? F 0 1 1 A and B
1 0 0 A or B
A>B?
1 0 1 not A

Y
Signal F control which function will be conducted by ALU.
Signal F is generated according to the current instruction.

Basic arithmetic operations: addition, subtraction,

Basic logic operations: and, or, xor, shifting,
Software Model of the 8086 Microprocessor
 Segmented Memory (x86 Style)
FFFFFh
Segment Registers:
Code
Segment
Point to Base Address
Segment
Registers
Extra
CS Segment Index Registers:
ES fragmentation
SS
DS
Stack
Segment
Contain Offset Value

Notation (Segmented Address):

Data
Segment
CS:IP
DS:SI
ES:DI
00000h SS:BP
System SS:SP
Memory
 Internal Architecture of 8086

8086 has two blocks BIU and EU.

 Bus Interface Unit
The BIU performs different functions such as
instruction fetching,
Instruction queuing
reading and writing operands for memory and
calculating the addresses of the memory operands.
Address relocation and Bus control.

BIU contains:
Instruction queue
Segment registers
Instruction pointer
Address adder.
 The instruction bytes are transferred to the
instruction queue.
BIU provides a full 16-bit bidirectional data
bus and 20-bit address bus.
The BIU is responsible for performing all
external bus operations.
The BIU uses a mechanism known as an
instruction stream queue to implement a
pipeline architecture.
Pipelined architecture of the 8086 microprocessors
 Pipelining Fetch Stage
Get Instruction From Memory
Store In Instruction Register

FETCH DECODE EXECUTE

Instruction #1
 Pipelining Decode Stage
Determine Instruction Type
Get Necessary Data
Setup ALU

FETCH DECODE EXECUTE

Instruction #2 Instruction #1
 Pipelining Execute Stage
Perform Required Operation
Store Result In Result Register

FETCH DECODE EXECUTE

Instruction #3 Instruction #2 Instruction #1

 Random-Access Memory
(RAM)
Scratch Pad

Stores Data and

Programs During
Execution

Only Retains Data

While Powered On
 Memory Segmentation
A segment is a 64KB block of memory starting from any 16-byte
boundary
For example: 00000, 00010, 00020, 20000, 8CE90, and E0840 are all valid
segment addresses
The requirement of starting from 16-byte boundary is due to the 4-bit
left shifting

Segment registers in BIU

15 0
CS Code Segment

DS Data Segment

SS Stack Segment

ES Extra Segment
 Read-Only Memory (ROM)
Instruction Manual

Data Doesnt Change

Used When System

Starts
 The queue permits pre fetch of up to six bytes of
instruction code.
When ever the queue of the BIU is not full, it has
room for at least two more bytes and at the
same time the EU is not requesting it to read or
write operands from memory, the BIU is free to
look ahead in the program by pre fetching the
next sequential instruction.
These pre fetching instructions are held in its
FIFO queue. With its 16 bit data bus, the BIU
fetches two instruction bytes in a single memory
cycle.
 After a byte is loaded at the input end of
the queue, it automatically shifts up
through the FIFO to the empty location
nearest the output.
The BIU also contains a dedicated adder
which is used to generate the 20-bit
physical address that is output on the
address bus.
This address is formed by adding an
appended 16-bit segment address and a
16-bit offset address.
 The physical address of the next
instruction to be fetched is formed by
combining the current contents of the
code segment CS register and the current
contents of the instruction pointer IP
register.
The BIU is also responsible for generating
bus control signals such as those for
memory read or write and I/O read or
write.
 Generating Memory Addresses
How can a 16-bit microprocessor generate 20-bit memory addresses?

Left shift 4 bits

FFFFF

16-bit register 0000 Addr1 + 0FFFF

Segment
+ 16-bit register Offset
Addr1
Offset
(64K)

20-bit memory address Segment

address
00000

Intel 80x86 memory address generation 1M memory space

 Memory Address Calculation

Segment addresses must be stored 0000

Segment address
in segment registers
Offset is derived from the combination + Offset

of pointer registers, the Instruction Memory address

Pointer (IP), and immediate values

Examples

CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction address 3 8 A B 4 Stack address 5 F F E 0

DS 1 2 3 4 0
DI + 0 0 2 2
Data address 1 2 3 6 2
 Fetching Instructions
Where to fetch the next instruction?
8088 Memory

CS 1234
IP 0012 12352 MOV AL, 0

12352

Update IP
After an instruction is fetched, Register IP is updated as follows:

IP = IP + Length of the fetched instruction

For Example: the length of MOV AL, 0 is 2 bytes. After fetching this instruction,
the IP is updated to 0014
 Accessing Data Memory
There is a number of methods to generate the memory address when
accessing data memory. These methods are referred to as
Addressing Modes
Examples:
Direct addressing: MOV AL, [0300H]

DS 1 2 3 4 0 (assume DS=1234H)
0 3 0 0
Memory address 1 2 6 4 0

Register indirect addressing: MOV AL, [SI]

DS 1 2 3 4 0 (assume DS=1234H)
0 3 1 0 (assume SI=0310H)
Memory address 1 2 6 5 0
 EXECUTION UNIT
The Execution unit is responsible for
decoding and executing all instructions.
EU contains:
Control circuitry
Instruction decoder
ALU
Pointer and Index registers
Flag register.
 EU Operation

1. Fetch an instruction from instruction

queue AH AL General purpose
BH BL register
2. According to the instruction, EU control CH CL
logic generates control signals. DH DL
(This process is also referred to as instruction SP
BP
decoding)
SI
DI ALU Data bus
3. Depending on the control signal, (16 bits)
EU performs one of the following
operations:
An arithmetic operation ALU
EU
A logic operation control instruction
Flag register 1011000101001010
Storing a datum into a register
Moving a datum from a register
Changing flag register
 The EU extracts instructions from the top of the
queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU
and requests it to perform the read or write bys
cycles to memory or I/O and perform the
operation specified by the instruction on the
operands.
During the execution of the instruction, the EU
tests the status and control flags and updates
them based on the results of executing the
instruction.
If the queue is empty, the EU waits for the next
instruction byte to be fetched and shifted to top
of the queue.
 When the EU executes a branch or jump
instruction, it transfers control to a location
corresponding to another set of sequential
instructions.
Whenever this happens, the BIU automatically
resets the queue and then begins to fetch
instructions from this new location to refill the
queue.
The EU accesses the queue from the output
end. It reads one instruction byte after the other
from the output of the queue. If the queue is full
and the EU is not requesting access to operand
in memory.
 These intervals of no bus activity, which
may occur between bus cycles are known
as Idle state.
If the BIU is already in the process of
fetching an instruction when the EU
request it to read or write operands from
memory or I/O, the BIU first completes the
instruction fetch bus cycle before initiating
the operand read / write cycle.
 PIN DIAGRAM
40 pin chip
8086 is designed to operate in two modes,
Minimum and Maximum.
Minimum Mode:
is selected by applying logic 1 to the MN / MX# input pin
Used for small systems
The 8086 provides all control signals needed to implement the
memory and I/O interface
The minimum mode signal can be divided into the following
basic groups :
1, Address/data bus,
2, Status,
3, Control,
4, Interrupt and DMA.
 Address/Data Bus
These lines serve two functions.
As an address bus is 20-bits long and
consists of signal lines A0 through A19.
A19 represents the MSB and A0 LSB.
A 20-bit address gives the 8086 a
1Mbyte memory address space. More
over it has an independent I/O address
space which is 64K bytes in length.
 The 16 data bus lines D0 through D15 are
actually multiplexed with address lines A0
through A15 respectively.
By multiplexed we mean that the bus work
as an address bus during first machine
cycle and as a data bus during next
machine cycles. D15 is the MSB and D0
LSB.
When acting as a data bus, they carry
read/write data for memory, input/output
data for I/O devices, and interrupt type
codes from an interrupt controller.
 Status signals

The four most significant address lines A19 through A16

are also multiplexed but in this case with status signals
S6 through S3.
These status bits are output on the bus at the same time
that data are transferred over the other bus lines.
Bit S4 and S3 together from a 2-bit binary code that
identifies which of the 8086 internal segment registers
are used to generate the physical address that was
output on the address bus during the current bus cycle.
Code S4S3 = 00 identifies a register known as extra
segment register as the source of the segment
address.
 Table
Status line S5 reflects the
status of another internal
characteristic of the 8086.
S4 S3 Segment register

It is the logic level of the internal

0 Extra
enable flag.
It gives the current setting of the 0 Stack
interrupt flag (IF) 0 Code/none
1 Data
1
The last status bit S6 is always 0
at the logic 0 level.
1
1
 Control Signals

The control signals are provided to support

The 8086 memory interface and
I/O interfaces.
They control functions such as
When the bus is to carry a valid address
In which direction data are to be transferred over
the bus
When valid write data are on the bus and
When to put read data on the system bus.
Control Signals are:
ALE
BHE/S7
M/IO
DT/R
RD
WR
DEN
READY
ALE

is a pulse to logic 1 that signals external

circuitry when a valid address word is on the
bus. This address must be latched in external
circuitry on the 1-to-0 edge of the pulse at
ALE.

Used to demultiplex AD15 - AD0 into A0 A15

and D0 D15 using external latches
 Using M/IO, DT/R and BHE/S7 control
signals Microprocessor signals:

Which type of bus cycle is in progress and

In which direction data are to be transferred
over the bus
M/IO
Logic level of M/IO tells external circuitry
whether a memory or I/O transfer is
taking place over the bus.
Logic 0 at this output signals a memory
operation
Logic 1 an I/O operation
DT/R
The direction of data transfer over the bus is signaled
by the logic level output at DT/R.
When this line is logic 1 during the data transfer part of
a bus cycle, the bus is in the transmit mode.Therefore,
data are either written into memory or output to an I/O
device.
On the other hand, logic 0 at DT/R signals that the bus
is in the receive mode. This corresponds to reading
data from memory or input of data from an input port.
Used to control data flow direction
If high: transmit data
If low: receives data
BHE/S7
Logic 0 on this line used as a memory enable signal
for the most significant byte half of the data bus D 8
through D15.
These lines also serves a second function, which is
as the S7 status line.
BHE is used to indicate the transfer of data over the
higher order(D15-D8) data bus
If low: at least one byte of the current
transfer is to be made on higher order
byte AD15-AD8
If High: transfer is made on lower order
byte AD7-AD0
 Table

BHE A0 Data Access

0 0 Word
0 1 Upper byte from an odd address
1 0 Lower byte from an even address
1 1 None
RD
indicates that the 8086 is performing a
read of data of the bus.
indicates that a read bus cycle is in
progress
If low: the microprocessor reads data from
memory or I/O device
WR
Indicates that a write bus cycle is in
progress.
8086 switches WR to logic 0 to signal
external device that valid write or output
data are on the bus.
i.e.,if low: microprocessor writes data into
memory or an I/O device
DEN
During read operations, one other control signal
called DEN is also supplied
it signals external devices when they should put
data on the bus.
This signal informs the transceivers that the
CPU is ready to send or receive data
The DEN signal indicates the direction of data,
i.e. from or to the processor. The system
contains memory for the monitor and users
program storage.
READY
There is one other control signal that is involved
with the memory and I/O interface that is READY
signal
is used to insert wait states into the bus cycle such
that it is extended by a number of clock periods.
This signal is provided by an external clock
generator device and can be supplied by the
memory or I/O subsystem to signal the 8086 when
they are ready to permit the data transfer to be
completed.
If low: 8086 enters into wait state
 is used primarily to synchronize
peripherals with the microprocessor
This is the acknowledgement from the
slow device or memory that they have
completed the data transfer.
The signal made available by the
devices is synchronized by the 8284A
clock generator to provide ready input
to the 8086. the signal is active high.
Interrupt Signals
INTR
INTA
TEST
NMI
RESET
INTR 8086
INTR
External
device

INTA

Data bus

Is the key interrupt interface

signal
is an input to the 8086 that can
be used by an external device
to signal that it need to be
serviced.
This is a triggered input
This is sampled during the last
clock cycles of each
instruction to determine the
availability of the request.
 Logic 1 at INTR represents an active
interrupt request.
When an interrupt request has been
recognized by the 8086, it indicates this
fact to external circuit with pulse to logic
0 at the INTA output.
This can be internally masked by
resulting the interrupt enable flag. This
signal is active high and internally
synchronized.
INTA
When an interrupt request has been
recognized by the 8086, it indicates this
fact to external circuit with pulse to logic
0 at the INTA output.
This signal is used as a read strobe for
interrupt acknowledge cycles. i.e. when
it goes low, the processor has accepted
the interrupt.
TEST
The TEST input is also related to the external
interrupt interface.
For ex: the execution of a WAIT instruction
causes the 8086 to check the logic
level at the TEST input.
If the logic 1 is found, the MPU suspends
operation and goes into the idle state.
The 8086 no longer executes instructions,
instead it repeatedly checks the logic level of
the TEST input waiting for its transition back to
logic 0.
 As TEST switches to 0, execution resume with
the next instruction in the program.
This feature can be used to synchronize the
operation of the 8086 to an event in external
hardware.
This signal is only used by the WAIT instruction,
MPU enters into a wait state after the execution
of the wait instruction until low signal on this pin
This input pin is examined by a WAIT
instruction.
If the TEST pin goes low, execution will continue,
else the processor remains in an idle state. The
input is synchronized internally during each clock
cycle on leading edge of clock.
NMI
Is a positive edge trigger NMI request
This is an edge triggered input which causes a
Type 2 interrupt.
The NMI is not maskable internally by software.
A transition from low to high initiates the interrupt
response at the end of the current instruction.
This input is internally synchronized.
On the 0-to-1 transition of NMI control is passed
to a non-maskable interrupt service routine at
completion of execution of the current instruction
RESET
The RESET input is used to provide a hardware
reset for the 8086.
Switching RESET to logic 0 initializes the internal
register of the 8086 and initiates a reset service
routine.
It causes the MPU to terminate the current activity
and start execution from FFF0H
The signal is active high and must be active for at
least four clock cycles.
It restarts execution when the RESET returns low.
RESET is also internally synchronized.
 DMA interface signals

This interface consists of HOLD and

HLDA signals.
HOLD
When an external device wants to take control of the
system bus, it signals to the 8086 by switching HOLD
to the logic 1 level.
At the completion of the current bus cycle, the 8086
enters the hold state.
In the hold state, signal lines
AD0 through AD15,
A16/S3 through A19/S6,
BHE, 8086 HOLD

M/IO, HLDA
Device 2

DT/R,
RD,
Bus
WR,
DEN and Memory
INTR are all in the high Z state.
 When the HOLD line goes high, it
indicates to the processor that another
master is requesting the bus access.
HLDA
The 8086 signals external device that it is in this
state by switching its HLDA output to logic 1 level.
The processor, after receiving the HOLD request,
issues the hold acknowledge signal on HLDA pin, in
the middle of the next clock cycle after completing
the current bus cycle.
At the same time, the processor floats the local bus
and control lines.
When the processor detects the HOLD line low, it
lowers the HLDA signal. HOLD is an asynchronous
input, and is should be externally synchronized.
 If the DMA request is made while the
CPU is performing a memory or I/O
cycle, it will release the local bus during
T4 provided:
The request occurs on or before T2 state of
the current cycle.
The current cycle is not operating over the
lower byte of a word.
The current cycle is not the first
acknowledge of an interrupt acknowledge
sequence.
A Lock instruction is not being executed.
 Minimum mode 8086 system
In a minimum mode 8086 system, the
microprocessor 8086 is operated in minimum
mode by strapping its MN/MX pin to logic 1.
In this mode, all the control signals are given out
by the microprocessor chip itself. There is a single
microprocessor in the minimum mode system.
The remaining components in the system are
latches,
transreceivers
clock generator
memory and I/O devices.
Some type of chip selection logic may be required
for selecting memory or I/O devices, depending
upon the address map of the system.
BUS Buffering and Latching
Latches
are generally buffered output D-type
flip-flops like 74LS373 or 8282.
They are used for separating the valid
address from the multiplexed
address/data signals and are controlled
by the ALE signal generated by 8086.
Transceivers
are the bi-directional buffers and some times they are
called as data amplifiers.
They are required to separate the valid data from the time
multiplexed address/data signals.
They are controlled by two signals namely,
DEN and
DT/R.
The DEN signal indicates the direction of data, i.e. from or
to the processor. The system contains memory for the
monitor and users program storage.
Usually, EPROM are used for monitor storage, while RAM
for users program storage.
 The clock generator generates the clock from
the crystal oscillator and then shapes it and
divides to make it more precise so that it can
be used as an accurate timing reference for
the system.
The clock generator also synchronizes some
external signal with the system clock. The
general system organization is as shown in
below fig.
It has 20 address lines and 16 data lines, the
8086 CPU requires three octal address
latches and two octal data buffers for the
complete address and data separation.
 The working of the minimum mode configuration
system can be better described in terms of the
timing diagrams rather than qualitatively
describing the operations.
The opcode fetch and read cycles are similar.
Hence the timing diagram can be categorized in
two parts, the first is the timing diagram for read
cycle and the second is the timing diagram for
write cycle.
The read cycle begins in T1 with the assertion of
ALE signal and also
M / IO signal.
During the negative going edge of this signal, the
valid address is latched on the local bus.
 The BHE and A0 signals address low, high or
both bytes.
From T1 to T4:
the M/IO signal indicates a memory or I/O operation.
At T2:
the address is removed from the local bus and is
sent to the output.
The bus is then tristated.
RD control signal is also activated in T2.
The read (RD) signal causes the address
device to enable its data bus drivers.
After RD goes low, the valid data is available on
the data bus.
 The addressed device will drive the READY
line high. When the processor returns the
read signal to high level, the addressed
device will again tristate its bus drivers.
A write cycle also begins with the assertion of
ALE and
the emission of the address.
The M/IO signal is again asserted to indicate a
memory or I/O operation.
In T2:
after sending the address in T1, the processor
sends the data to be written to the addressed
location.
 The data remains on the bus until middle of
T4 state.
The WR becomes active at the beginning of
T2 (unlike RD is somewhat delayed in T2 to
provide time for floating).
The BHE and A0 signals are used to select
the proper byte or bytes of memory or I/O
word to be read or write.
The M/IO, RD and WR signals indicate the
type of data transfer as specified in table
below.
 Data Transfer table

M / IO RD WR Transfer Type
0 0 1 I / O read
0 1 0 I/O write
1 0 1 Memory read
1 1 0 Memory write
 Hold Response sequence:
The HOLD pin is checked at leading edge of each
clock pulse.
If it is received active by the processor before T4
of the previous cycle or during T1 state of the
current cycle, the CPU activates HLDA in the next
clock cycle and for succeeding bus cycles, the bus
will be given to another requesting master.
The control of the bus is not regained by the
processor until the requesting master does not
drop the HOLD pin low
When the request is dropped by the requesting
master, the HLDA is dropped by the processor at
the trailing edge of the next clock.
 Maximum Mode Interface
When the 8086 is set for the maximum-mode
configuration, it provides signals for
implementing a multiprocessor / coprocessor
system environment.
By multiprocessor environment we mean that
one microprocessor exists in the system and
that each processor is executing its own
program.
Coprocessor also means that there is a second
processor in the system. In this two processor
does not access the bus at the same time.
One passes the control of the system bus to the
other and then may suspend its operation.
 In this mode the available pins:
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
QS0
QS1
This mode uses :
Bus controller(8288)
Bus arbiter(8289)
Queue status signals
Local bus control signals
 8288 Bus Controller

Separate signals are used for I/O ( IORC and IOWC ) and memory ( MRDC and MWTC ).

Also provided are advanced memory ( AIOWC ) and I/O ( AIOWC ) write strobes plus INTA .
Bus Controller(8288)
It provides
Bus Command and
Control Signals
8086 does not directly provide all the signals that
are required to control
the memory
I/O and
Interrupt interfaces.
Specially the
WR,
M/IO,
DT/R,
DEN,
ALE and
INTA, signals are no longer produced by the 8086.
 Instead it outputs three status signals:
S0, S1, S2 prior to the initiation of each bus
cycle.
This 3- bit bus status code
identifies which type of bus cycle is to follow.
S2S1S0 are input to the external bus
controller device
The bus controller generates
the appropriately timed command and
control signals.
 Bus Status Codes
Status Inputs CPU Cycles 8288
S2 S1 S0 Command

0 0 0 Interrupt Acknowledge INTA

0 0 1 Read I/O Port IORC
0 1 0 Write I/O Port IOWC,AIOWC
0 1 1 Halt None
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC,AMWC
1 1 1 Passive None
 The 8288 produces
one or two of these eight command signals for each bus
cycles.
For instance:
when the 8086 outputs the code S2S1S0 equals 001, it
indicates that an I/O read cycle is to be performed.
In the code 111 is output by the 8086, it is signaling that no
bus activity is to take place.
The control outputs produced by the 8288 are
DEN,
DT/R and
ALE.
These 3 signals provide the same functions as
those described for the minimum system mode.
8289 Bus Arbiter
It provides
Bus Arbitration and
Lock Signals
This device permits processors to reside on the
system bus.
It does this by implementing the Multi bus
arbitration protocol in an 8086-based system.
Addition of
the 8288 bus controller and
8289 bus arbiter
frees a number of the 8086 pins for use
to produce control signals that are needed to support
multiple processors.
LOCK: Bus priority lock
is one of these signals.
It is input to
the bus arbiter together with
status signals S0 through S2.
When LOCK signal is low:
It indicates that other system bus masters will be
prevented from gaining the system bus.
Bus Arbitration

The output of 8289 are bus arbitration signals:

bus busy(BUSY),
common bus request (CBRQ),
bus priority out(BPRO),
bus priority in (BPRN),
bus request (BREQ) and
bus clock (BCLK).
They correspond to
the bus exchange signals of the Multi bus and
are used to lock other processor off the system bus during
the execution of an instruction by the 8086.
Queue Status Signals
are queue status outputs QS0 and QS1.
Together they form a 2-bit queue status
code, QS1QS0.
This 2-bit queue status code tells the
external circuitry what type of
information was removed from the queue
during the previous cycle.
Following table shows the four different
queue status
 Queue status codes

QS1 QS0 Queue Status

0 0 No Operation. During the last clock cycle,
nothing was taken from the queue.

0 1 First Byte. The byte taken from the queue

was the first byte of the instruction.

1 0 Queue Empty. The queue has been

reinitialized as a result of the execution of a
transfer instruction.

1 1 Subsequent Byte. The byte taken from the

queue was a subsequent byte of the
instruction.
Local Bus Control Signal
Are Request / Grant Signals
In maximum mode configuration, the minimum mode
HOLD, HLDA interfaces are replaced by request/grant
lines RQ/ GT0 and RQ/ GT1, respectively.
They provide a prioritized bus access mechanism for
accessing the local bus.
These pins are used by other local bus masters to
force the CPU to release the local bus at the end of the
CPUs current bus cycle.
Each pin is a bi-directional
RQ/ GT0 having higher priority than RQ/ GT 1
 RQ/GT
By using RQ signal another master can request
for the system bus and
The microprocessor communicate that the
request is granted to the requesting master by
using bus grant signal.
Both these signals are similar except the
RQ/GT0 has higher priority than RQ/GT1
 Minimum and Maximum Operation modes
Intel 8088 (8086) has two operation modes:

Minimum Mode Maximum Mode

8088 generates control signals It needs 8288 bus controller to generate

for memory and I/O operations control signals for memory and I/O
operations

Some functions are not available It allows the use of 8087 coprocessor;
in minimum mode it also provides other functions

Compatible with 8085-based

systems
 System Time Diagrams - CPU Bus Cycle
CLK T1 T2 T3 TW T4

ALE Address latches store the actual values

IO/M Memory Cycle (I/O cycle is similar but IO/M = 1)
A16- A19 A16-A19 S3- S6
A8- A15 A8- A15
READY the P samples READY
The slow device drives READY= 0 (if 0 a WAIT state follows)
Read Cycle
RD (instruction fetch and memory operand read) P reads Data Bus
AD0- AD7 A0- A7 D0- D7 (Data in)
Tri-state
DT/R Direction READ for the Data Buffer
DEN Enables Data Buffer
Memory reads Data Bus
WR Write Cycle (memory operand write)
AD0- AD7 A0- A7 D0- D7 (Data out)
DT/R Direction READ for the Data Buffer
DEN Enables Data Buffer
Timing Diagram : 8086 Read Cycle
T1 T2 T3 T4

CLK

/S0, /S1, /S2 001 or 101

A16..A19, /BHE Address Status

S3..S6

ALE

float float
AD0..AD15 Address Valid Data

A0..A19 Valid Address

DT/R

DEN

/MRDC or /IORC
Read Cycle
Timing Diagram : 8086 Write Cycle
T1 T2 T3 T4

CLK

/S0, /S1, /S2 010 or 110

A16..A19, /BHE Address Status

S3..S6

ALE

AD0..AD15 Address Valid Data

A0..A19 Valid Address

DT/R

DEN

/MWTC or /IOWC
Write Cycle
8086 Read Cycle (1 Wait State)
T1 T2 T3 Tw T4

CLK

/S0, /S1, /S2 001 or 101

A16..A19, /BHE Address Status

S3..S6

ALE

8284 RDY

READY

float float
AD0..AD15 Address Valid Data

A0..A19 Valid Address

DT/R

DEN

/MRDC or /IORC
 Register organization
The 8086 has four groups of the user
accessible internal registers.
The 8086 has a total of fourteen 16-bit
registers
Classification of registers:
General purpose registers
Special purpose registers
Flag register
Pointer and index registers
General purpose Registers:
All general purpose registers of the 8086
microprocessor can be used for arithmetic
and logic operations.
The general purpose registers are:
Accumulator
Base register
Counter register
Data register
 General Purpose Registers
15 8 7 0
AX AH AL Accumulator

BX BH BL Base
Data Group
CX CH CL Counter

DX DH DL Data

SP Stack Pointer

BP Base Pointer
Pointer and
Index Group
SI Source Index

DI Destination Index
Accumulator

This register consists of

two 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX.
AL in this case contains the low-order byte of the word and
AH contains the high-order byte
Accumulator can be used for
I/O operations and
string manipulation.
Provides one of the operand
Also holds the result of operation
User can access this register
Base Register
Base register consists of two 8-bit registers BL and
BH
which can be combined together and used as a
16-bit register BX.
BL in this case contains the low-order byte of the
word, and BH contains the high-order byte.
BX register usually contains a data pointer used
for
based,
based indexed or
register indirect addressing.
 Is used as a pointer
Used as a offset storage register(in certain
addressing modes) for all segment
memories (CS,DS,SS&ES)
Used for reading data from memory
Or, writing data into memory
8086 has to select 1 memory location ,the
16-bit effective address(EA) of this
memory location can be stored in BX
register
Counter Register
Count register consists of two 8-bit registers
CL and CH, which can be combined together
and used as a 16-bit register CX.
When combined, CL register contains the
low-order byte of the word, and CH contains
the high order byte.
Count register can be used in
Loop, shift/rotate instructions and
as a counter in string manipulation
 Used as a counter
CL: used as a 8-bit counter for
Rotate,
Shift instructions and stores 8-bit count
CX: used as 16-bit implicit counter for
REP(repeat)
Loop instructions
Data Register
Data register consists of two 8-bit registers DL
and DH, which can be combined together and
used as a 16-bit register DX.
When combined, DL register contains the low-
order byte of the word, and DH contains the high
order byte.
Data register can be used as
a port number in I/O operations.
In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or resulting
number.
 Used for multiplication and division
instructions
In order to store 32-bit data or result,
DX and AX registers are used together
DX register is used to store 16MSB
AX register is used to store 16LSB
Special Purpose Registers
This group consists of four 16-bit registers,
these are classified as:
Code Segment Register
Stack Segment Register
Data Segment register
Extra Segment Register
Code Segment Register
It holds the starting address of Code segment memory
The processor uses CS segment for all accesses to
instructions referenced by instruction pointer (IP)
register.
i.e., IP holds offset value
CS register cannot be changed directly.
The CS register is automatically updated during
far jump,
far call and
far return instructions.
CS:IP/BX
Stack Segment Register

Is a 16-bit register used to hold the

starting(base) address of stack memory.
By default, the processor assumes that all data
referenced by
the stack pointer (SP) and
base pointer (BP) registers is located in the stack segment.
SP or BP is used to hold the offset value
SS register can be changed directly using POP
instruction.
SS:SP/BP/BX
Data Segment Register

It holds the starting address of DS memory

By default, the processor assumes that all data
referenced by general registers (AX, BX, CX, DX) and
index register (SI, DI) is located in the data segment.
i.e., any one of AX,BX,CX,DX,SI and DI these
registers holds offset value (that depends on the type
of addressing)
DS register can be changed directly using
POP and
LDS instructions.
DS:SI/BP/DI/BX
Extra Segment Register

Is a 16-bit register, holds the starting address of

extra segment memory
By default, the processor assumes that the DI
register references the ES segment in string
manipulation instructions.
i.e., DI register is used to hold the offset value
ES register can be changed directly using
POP and
LES instructions.
ES:DI/BX
Generation of 20-bit address
8086 generates 20-bit address by adding base
address(after shifting it by 4 bits left) and offset address
Offset address is present in memory pointers(IP)
For this pointer there is a fixed segment register for base
address
This fixed segment register of memory pointers is called as
default segment registers
Apart from actual segment register 8086 can take base
address from other segment registers
But the programmer has to specify the name of these
registers in the instruction.hence these registers are called
specified segment registers.
Pointer and Index Register

are 16- bit registers,

used for offset storage
classified as
Stack Pointer
Base Pointer
Source Index
Destination Index
Instruction Pointer
 Stack Pointer:
is a 16-bit register pointing to program stack.
holds the address of stack top i.e., the upper most filled
memory location in stack memory
Contents of SP can be decremented/incremented after each
stack read operation
Base Pointer:
is a 16-bit register pointing to data in stack segment.
BP register is usually used for
based,
based indexed or
register indirect addressing.
Its use is similar to SI &DI
Acts as a memory pointer to SS register
Mainly used to access any location directly in the
stack
Source Index:
is a 16-bit register.
SI is used for
indexed,
based indexed and
register indirect addressing, as well as
a source data address in string manipulation instructions.
Destination Index:
is a 16-bit register.
DI is used for
indexed,
based indexed and
register indirect addressing, as well as
a destination data address in string manipulation instructions.
 Both SI and DI can be used
for general purpose registers as well as
for Offset storage
Both SI and DI act as memory pointers
relative to DS
Microprocessor takes EA of data from SI and
stores in DI
Instruction Pointer:
is a 16-bit register.
is also used to hold offset value
Contains offset of the next instruction
Points to the next instruction to be fetched from CS
Program Counter:
Holds the address of an instruction which is to be
executed next
When reset is activated, PC is set to the address of
the first instruction to be fetched
The content of PC is auto incremented
So, offset value may be the content of
SP,BP,SI,DI,IP or BX or an immediate 16-bit
value depending on addressing mode
CS:IP/BX
SS:SP/BP/BX
DS:SI/BP/DI/BX
ES:DI/BX
 Flag register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- NT IOPL OF DF IF TF SF ZF - AF - PF - CF

CF Carry Flag Contains Carry out of MSB of result

PF Parity Flag Indicates if result has even parity
AF Auxiliary carry Flag Contains Carry out of bit 3 in AL
ZF Zero Flag Indicates if result equals zero
SF Sign Flag Indicates if result is negative
TF Trace Flag Provides a single step capability for debugging
IF Interrupt enable Flag Enables/disables interrupts
DF Direction Flag Controls pointer updating during string operations
OF Overflow Flag Indicates that an overflow occurred in result
IOPL I/O Priority Level Priority level of current task (two bits)
NT Nested Task Indicates if current task is nested
 Flag Register
Flag register contains information reflecting the current status of a
microprocessor. It also contains information which controls the
operation of the microprocessor.
15 0
NT IOPL OF DF IF TF SF ZF AF PF CF

Control Flags Status Flags

IF: Interrupt enable flag CF: Carry flag

DF: Direction flag PF: Parity flag
TF: Trap flag AF: Auxiliary carry flag
ZF: Zero flag
SF: Sign flag
OF: Overflow flag
NT: Nested task flag
IOPL: Input/output privilege level
Flag Register

After an execution of instruction, the

microprocessor produces some conditions,
which are indicated by flag register
Contains the information reflecting the current
status of a microprocessor
Or, it provides information about the last
executed instruction
Also contains the information which controls the
operation of the microprocessor
is a 16-bit register containing 9 one bit flags.
 This flag register can be divided into 2 types
of flags
Control flags and
Status flags
Control flags:
Are DF,IF and TF
Depend upon the value of controlling flag bit
Microprocessor controls particular operation
Status flags:
The remaining flags of flag register(other than control
flags)
Show the status of result
Carry Flag:

Set if there was a carry from or borrow to the

most significant bit during last result calculation.
Or
Set when the result of an unsigned arithmetic
operations too large to fit into the destination
Indicates
carry after after addition or
Borrow after subtraction
Parity Flag:

Indicates if the result has even parity.

Or
Set if parity (the number of "1" bits) in the
low-order byte of the result is even.

Parity:
Means counting of number of 1s in the unit of
data
Could be even number or odd number
Auxiliary carry flag:

This bit is set when a carry is generated

by bit 3 and passed on to bit4
Or
Set when the result of an operation
causes a carry from bit 3 to 4
Contains carryout of bit 3 in AL
Zero flag:

set if the result of an arithmetic or logical

operation is zero.
Or
Set if ALU operation result is zero
Sign flag:
Indicates if the result is Negative.
Trace flag:
Provides a single step capability for
debugging
Determines whether or not the CPU is
halted after each instruction.
It allows programmers to do tracing
if set, then single-step interrupt will occur
after the next instruction.
Interrupt enable flag:

Enables/disables interrupts
Dictates whether or not system interrupt
can occur if logic 1:enabled
0:disabled
Or, Setting this bit enables maskable
interrupts.
Direction flag:

Controls pointer updating

Affects block data transfer instructions
such as MOVS,CMPS during string
operations
If logic1: enabled
If logic0: disabled
Overflow flag:

Indicates that an overflow occurred in result

Set when the result of a signed arithmetic
operation is too wide to fit into the destination
Or
is a condition that can occur when signed
numbers are added or subtracted
Or
Set if the result is too large positive number, or is
too small negative number to fit into destination
operand.
I/O Priority Level:

Indicates the priority level of current

task

Nested Task:
Indicates if current task is nested
 Addressing modes
Immediate
Direct
Register
Register indirect
Indexed
Register relative
Based index
Relative based index
Immediate Addressing

MOV AX,0005H
Copies 0005H into AX
the data is provided in the instruction.
Direct addressing:
the instruction operand specifies the
memory address where data is located.
MOV AX,[5000H]
Copies the contents of data segment
memory location 5000H into AX
Physical address: 10*DS+5000H
Register addressing

references the data in a register or in a

register pair.
MOV BX,AX
Copies AX into BX
Register indirect addressing
instruction specifies a register containing an address,
where data is located. This addressing mode works with
SI, DI, BX and BP registers.
Means: addressing data at any location through an offset
address held in SI, DI, BX and BP registers
MOV AX,[BX]
Physical address: 10H*DS+[BX]
Copies the word contents of the data segment memory
location address by BX into AX
Another ex: MOV [DI],BH
Copies BH into the data segment memory location
addressed by DI
SI/DI can also be used in the room of BX
Indexed addressing mode

8-bit or 16-bit instruction operand is added

to the contents of an index register (SI or
DI), the resulting value is a pointer to
location where data resides
MOV AX,[SI]
Physical address: 10H*DS+[BX]
DI can also be used in the room of SI
Register relative
MOV AX, 50H[BX] or MOV AX, [BX+50H]
Copies the contents of data segment
memory location addressed by the sum of
BX,50H into AX
BX/BP/SI/DI
 Based index
the contents of a base register (BX or BP) is
added to the contents of an index register (SI or
DI), the resulting value is a pointer to location
where data resides.
MOV AX,[BX+SI] or MOV AX, [BX][SI]
Copies the word contents of the data segment
memory location address by BX plus SI into AX
MOV [BX+SI],SP
Copies SP into the data segment memory
location address by BX plus SI
 Relative based index
MOV AX,50H[BX][SI]
Copies the contents of data segment
memory location addressed by the sum of
BX,SI and 50H into AX
8-bit or 16-bit instruction operand is added
to the contents of a base register (BX or
BP) and index register (SI or DI), the
resulting value is a pointer to location
where data resides.
Instruction Set
 Software
The sequence of commands used to tell a
microcomputer what to do is called a program,
Each command in a program is called an instruction
8086 understands and performs operations for 117 basic
instructions
The native language of the IBM PC is the machine
language of the 8086
A program written in machine language is referred to as
machine code
In 8086 assembly language, each of the operations is
described by alphanumeric symbols instead of 0-1s.
ADD AX, BX

(Opcode) (Destination operand) (Source operand )

 Software: From Machine to
High-Level Languages
Machine Language: binary instructions
Difficult to decipher and write
Prone to cause many errors in writing
All programs converted into the machine
language of a processor for execution
Instructio Hex Mnemoni Description Processor
n c
10000000 80 ADD B Add reg B to Acc Intel 8086
00101000 28 ADD A, R0 Add Reg R0 to Acc Intel 8051
00011011 1B ABA Add Acc A and B Motorola6811
 Software: From Machine to
High-Level Languages
Assembly Language: machine instructions
represented in mnemonics
Has one-to-one correspondence with machine
instructions
Efficient in execution and use of memory;
machine-specific and not easy to troubleshoot
 Software: From Machine to
High-Level Languages
High-Level Languages (such as BASIC, C,
and C++)
Written in statements of spoken languages
(such as English)
machine independent
easy to write and troubleshoot
requires large memory and less efficient in
execution
 8086 Instruction Sets 7 type
1. Data Transfer
2. Arithmetic
3. Bit Manipulation
4. Control Transfer or Branch
5. String instructions
6. Interrupt Instructions
7. Processor Control
 8086 Instruction Sets 7 Types
1. Data Transfer
General purpose Address Object
MOV LEA
PUSH LDS
POP LES
XCHG Flag Transfer
XLAT LAHF
Input/Output SAHF
IN PUSHF
OUT POPF
 Data transfer instructions
8086 instruction set Additional 80386 instructions
IN Input byte or word from port LFS Load pointer using FS
LAHF Load AH from flags LGS Load pointer using GS
LDS Load pointer using data segment LSS Load pointer using SS
LEA Load effective address MOVSX Move with sign extended
LES Load pointer using extra segment MOVZX Move with zero extended
MOV Move to/from register/memory POPAD Pop all double (32 bit) registers
OUT Output byte or word to port POPD Pop double register
POP Pop word off stack POPFD Pop double flag register
POPF Pop flags off stack PUSHAD Push all double registers
PUSH Push word onto stack PUSHD Push double register
PUSHF Push flags onto stack PUSHFD Push double flag register
SAHF Store AH into flags
XCHG Exchange byte or word
XLAT Translate byte
Additional 80486 instruction
Additional 80286 instructions BSWAP Byte swap
INS Input string from port
OUTS Output string to port Additional Pentium instruction
POPA Pop all registers MOV Move to/from control register
PUSHA Push all registers
 Data Transfer Instructions - MOV
Mnemonic Meaning Format Operation Flags
affected
Mov Move Mov D,S (s) (D) None

Destination Source
Memory Accumulator
Accumulato Memory
r
Register Register NO MOV
Register Memory
Memory Register Mem
Mem
Register Immediate Imm Seg Reg
Memory Immediate Seg Reg Seg reg
Seg reg Reg 16
Seg reg Mem 16
Reg 16 Seg reg EX: MOV AL, BL
Memory Seg reg
 Data Transfer Instructions - XCHG

Mnemonic Meaning Format Operation Flags affected

XCHG Exchange XCHG D,S (s) (D) None

Destination Source

Accumulator Reg 16
Example: XCHG [1234h], BX
Memory Register

Register Register
NO XCHG
MEMs
Register Memory
SEG REGs
The Stack
The stack is used for temporary storage of information such as data or
addresses; for instance when a CALL is executed the 8088
automatically PUSHes the current value of CS and IP onto the stack.
Other registers can also be pushed
Before return from the subroutine, POP instructions can be used to pop
values back from the stack into the corresponding registers
Example for PUSH
Example for POP
 Data Transfer Instructions LEA, LDS,
LES
Mnemonic Meaning Format Operation Flags
affected
LEA Load LEA Reg16,EA EA (Reg16) None
Effective
Address
LDS Load LDS Reg16,MEM32 (MEM32) None
Register (Reg16)
And DS
(Mem32+2) (DS)

LES Load LES Reg16,MEM32 (MEM32) None

Register (Reg16)
and ES
(Mem32+2) (DS)

LEA SI DATA or MOV SI Offset DATA

 Examples for LEA, LDS, LES

LES similar to LDS except that it loads ES

 Examples for LEA, LDS, LES
DATAX DW 1000H
DATAY DW 5000H
.CODE
LEA SI, DATAX
MOVE DI, OFFSET DATAY; THIS IS MORE EFFICIENT
LEA BX,[DI]; IS THE SAME AS
MOV BX,DI; THIS JUST TAKES LESS CYCLES.
LEA BX,DI; INVALID!

LDS BX, [DI];

7A 11000
BX 127A 12 11001
00
DI 1000 11002
30
11003
DS 3000

LES similar to LDS except that it loads ES

The XLAT Instruction
Mnemonic Meaning Format Operation Flags
XLAT Translate XLAT ((AL)+(BX)+ None
(DS)0)
(AL)

Example: Assume (DS) = 0300H, (BX)=0100H, and

(AL)=0DH
XLAT replaces contents of AL by contents of memory location with
PA=(DS)0 +(BX) +(AL)
= 03000H + 0100H + 0DH = 0310DH
Thus
(0310DH) (AL)
 2. Arithmetic instructions
8086 instruction set Additional 80386 instructions
AAA ASCII adjust for addition CDQ Convert double-word to
AAD ASCII adjust for division quad-word
AAM ASCII adjust for multiply CWDE Convert word to double-word
AAS ASCII adjust for subtraction
ADC Add byte or word plus carry
Additional 80486 instructions
ADD Add byte or word
CMPXCHG Compare and exchange
CBW Convert byte or word
XADD Exchange and add
CMP Compare byte or word
CWD Convert word to double-word
DAA Decimal adjust for addition
Additional Pentium instruction
DAS Decimal adjust for subtraction
CMPXCHG8B Compare and
DEC Decrement byte or word by one
exchange 8 bytes
DIV Divide byte or word
IDIV Integer divide byte or word
IMUL Integer multiply byte or word
INC Increment byte or word by one
MUL Multiply byte or word (unsigned)
NEG Negate byte or word
SBB Subtract byte or word and carry (borrow)
SUB Subtract byte or word
 8086 Instruction Sets 7 Types
Arithmetic
Addition Subtraction
SUB
ADD SBB
ADC DEC
INC NEG
CMP
AAA AAS
DAA DAS
Multiplication Division
DIV
MUL IDIV
IMUL AAD
AAM CBW
CWD
 Arithmetic Instructions
ADD, ADC, INC, AAA, DAA

Mnemonic Meaning Format Operation Flags

affected
ADD Addition ADD D,S (S)+(D) (D) ALL
carry (CF)
ADC Add with ADC D,S (S)+(D)+(CF) (D) ALL
carry carry (CF)
INC Increment INC D (D)+1 (D) ALL but CY
by one
AAA ASCII AAA If the sum is >9, AH AF,CF
adjust for is incremented by 1
addition

DAA Decimal DAA Adjust AL for decimal ALL

adjust for Packed BCD
addition
 Examples:
Ex.1 ADD AX,2
ADC AX,2

Ex.2 INC BX
INC WORD PTR [BX]

Ex.3 ASCII CODE 0-9 = 30-39h

MOV AX,38H; (ASCII code for number 8)
ADD AL,39H; (ASCII code for number 9) AL=71h
AAA; used for addition AH=01, AL=07
ADD AX,3030H; answer to ASCII 0107 AX=3137

Ex.4 AL contains 25 (packed BCD)

BL contains 56 (packed BCD) 25
ADD AL, BL + 56
DAA --------
7B 81
Example: .MODEL SMALL ; program that adds two multiword numbers:
.STACK 64
.DATA
DATA1 DQ 548F9963CE7h ;allocate 8 bytes
ORG 0010h
DATA2 DQ 3FCD4FA23B8Dh ; allocate 8 bytes
ORG 0020h
DATA3 DQ ?
.CODE
MAIN PROC FAR
MOV AX,@DATA ; receive the starting address for DATA
MOV DS,AX
CLC ; clear carry
MOV SI,OFFSET DATA1 ; LEA for DATA1
MOV DI,OFFSET DATA2 ; LEA for DATA2
MOV BX,OFFSET DATA3 ; LEA for DATA3
MOV CX,04h
BACK: MOV AX,[SI]
ADC AX,[DI] ; add with carry to AX
MOV [BX],AX
ADD SI,2h
ADD DI,2h
ADD BX,2h
LOOP BACK ; decrement CX automatically until zero
MOV AH,4Ch
INT 21h; halt
MAIN ENDP
END MAIN
 Arithmetic Instructions
Mnemonic Meaning Format Operation Flags
affected
SUB Subtract SUB D,S (D)-(S) (D) All
Borrow (CF)
SBB Subtract SBB D,S (D)-(S)-(CF) (D) All
with
borrow
DEC Decrement DEC D (D)-1 (D) All but CF
by one
NEG Negate NEG D All

DAS Decimal DAS Convert the result in AL to All

adjust for packed decimal format
subtraction
AAS ASCII AAS (AL) difference CY,AC
adjust for (AH) dec by 1 if borrow
subtraction
 Assume (BX)=003AH, what is the result of
executing the instruction
NEG BX

(BX)=0000000000111010
2s comp = 1111111111000110 = FFC6H
(CF)=1
Example

32-bit subtraction of two 32 bit numbers X and Y that are

stored in the memory as
X = (DS:203h)(DS:202h)(DS:201h)(DS:200h)
Y = (DS:103h)(DS:102h)(DS:101h)(DS:100h)
The result X - Y to be stored where X is saved in the
memory
MOV SI, 200h
MOV DI, 100h
MOV AX, [SI]
SUB AX, [DI]
MOV [SI], AX ;save the LS word of result
MOV AX, [SI] +2
SBB AX, [DI]+2
MOV [SI] +2, AX
Ex. 12 34 56 78 23 45 67 89 = EF EE EE EE
Multiplication and Division
 OUT/IN instruction
port address: 50H
2050 D3 OUT 50H sends acc content to I/O address 50H
2051 50
Let input port address is 30H
2150 DB IN 30H reads content from I/O address 30H and
2151 30 stores the value in accum
 3. Bit manipulation instructions

8086 instruction set Additional 80386 instructions

AND Logical AND of byte or word BSF Bit scan forward
NOT Logical NOT of byte or word BSR Bit scan reverse
OR Logical OR of byte or word BT Bit test
RCL Rotate left trough carry byte or word BTC Bit test and complement
RCR Rotate right trough carry byte or word BTR Bit test and reset
ROL Rotate left byte or word BTS Bit test and set
ROR Rotate right byte or word SETcc Set byte on condition
SAL Arithmetic shift left byte or word SHLD Shift left double precision
SAR Arithmetic shift right byte or word SHRD Shift right double precision
SHL Logical shift left byte or word
SHR Logical shift right byte or word
TEST Test byte or word
XOR Logical exclusive-OR of byte or word
 8086 Instruction Sets 7 Types
Bit Manipulation
Logicals Rotates
NOT ROL
AND
ROR
OR
XOR RCL
TEST RCR
Shifts
SHL/SAL
SHR
SAR
Logical Instructions
 Logical Instructions
AND
Uses any addressing mode except memory-to-
memory and segment registers
Especially used in clearing certain bits (masking)
xxxx xxxx AND 0000 1111 = 0000 xxxx
(clear the first four bits)
Examples: AND BL, 0FH
AND AL, [345H]

OR
Used in setting certain bits
xxxx xxxx OR 0000 1111 = xxxx 1111
(Set the upper four bits)
 XOR
Used in inverting bits
xxxx xxxx XOR 0000 1111 = xxxxxxxx
-Example: Clear bits 0 and 1, set bits 6 and 7, invert bit
5 of register CL:
AND CL, OFCH ; 1111 1100B
OR CL, 0C0H ; 1100 0000B
XOR CL, 020H ; 0010 0000B
Shift Instructions
 Shift Instructions

Destination Count

Register 1

Register CL

Memory 1

Memory CL
 Ex.
; Multiply AX by 10
SHL AX, 1
MOV BX, AX
MOV CL,2
SHL AX,CL
ADD AX, BX
Ex. What are the results of SAR CL, 1
if CL initially contains B6H? DBH
Ex. What are the results of SHL AL, CL
if AL contains 75H and CL contains 3? A8H
Rotate Instructions
Rotate Instructions

Destination Count

Register 1

Register CL

Memory 1

Memory CL
Ex. What is the result of ROL BTRE PTR [SI], 1
if SI is pointing to a memory location that contains 41H? (82H)
 Example
Write a program that counts the number of 1s in a
byte and writes it into BL
DATA1 DB 97 ; 61h
SUB BL, BL ; clear BL to keep the number of 1s
MOV DL, 8 ; Counter
MOV AL, DATA1
AGAIN: ROL AL,1 ; rotate left once
JNC NEXT ; check for 1
INC BL ; if CF=1 then add one to count
NEXT: DEC DL ; go through this 8 times
JNZ AGAIN ; if not finished go back
NOP
 8086 Instruction Sets 7 Types
4. Control Transfer
Conditional Transfers Conditional Transfers(continue)
JA/JNBE JNS
JAE/JNB JO
JB/JNAE
JP/JPE
JBE/JNA
JS
JC
JE/JZ Unconditional Transfers
JG/JNLE CALL
JGE/JNL RET
JL/JNGE JMP
JLE/JNG Iteration Controls
JNC LOOP
JNE/JNZ LOOPE/LOOPZ
JNO LOOPNE/LOOPNZ
JNP/JPO JCXZ
 5. String instructions
8086 instruction set
CMPS Compare byte or word string
LODS Load byte or word string
MOVS Move byte or word string
MOVSB(MOVSW) Move byte string (word string)
REP Repeat
REPE (REPZ) Repeat while equal (zero)
REPNE (REPNZ) Repeat while not equal (not zero)
SCAS Scan byte or word string
STOS Store byte or word string
 8086 Instruction Sets 7 Types
6.Interrupt Instructions
INT
INTO
IRET
 8086 Instruction Sets 7 Types
7. Process Control
Flag Operations External Synchronization
STC HLT
LCL WAIT
CMC ESC
STD LOCK
CLD No Operations
STI NOP
CLI
ASSEMBLER DIRECTIVES
or
Pseudo-Operations
Depending upon the operation performed
by these assembler directives they are
classified into:
Data definition & storage allocation
directives
-DB (define byte)
-DW (define word)
-DD (define double word)
-DQ (define quadrant)
-DT (define ten bytes)
-STRUC (define structure)
 Program Organization Directives:
-SEGMENT (logical segment)
-ENDS (end of segment)
-ASSUME (assume logical segment name)

Alignment Directives:
-EVEN (align on even memory address)
-ORG (origin)

Program end directives :

-END (end of program)
 Value returning attribute directives:
-OFFSET (offset of a label)
-SIZE (size)

Procedure definition directives:

-PROC (procedure)
-ENDP (end of procedure)
 Data control directive:
-PUBLIC (public)
-EXTRN (external)
-PTR (pointer)

Branch displacement directive:

-SHORT
-LABEL
-NEARFAR
Assume directive:
The ASSUME directive is used to tell the assembler that
the name of the logical segment should be used for a
specified segment.
The 8086 works directly with only 4 physical segments: a
Code segment, a data segment, a stack segment, and
an extra segment.
Example:
ASUME CS:CODE ; This tells the assembler that the logical
segment named CODE contains the instruction statements for
the program and should be treated as a code segment.
ASUME DS:DATA ; This tells the assembler that for any
instruction which refers to a data in the data segment, data will
found in the logical segment DATA.
 DB: DB directive is used to declare a byte-type
variable or to store a byte in memory location.
Example:
1. PRICE DB 49h, 98h, 29h ; Declare an array of 3
bytes; named as PRICE and initialize.
2. NAME DB ABCDEF ; Declare an array of 6 bytes
and; initialize with ASCII code for letters
3. TEMP DB 100 DUP(?) ; Set 100 bytes of storage in
memory and give it the name as TEMP, but leave the
100 bytes uninitialized. Program instructions will load
values into these locations.
 DW: The DW directive is used to define a
variable of type word or to reserve storage
location of type word in memory.
Example:
MULTIPLIER DW 437Ah ; this declares a variable of
type word and named it as MULTIPLIER. This
variable is initialized with the value 437Ah when it is
loaded into memory to run.
EXP1 DW 1234h, 3456h, 5678h ; this declares an
array of 3 words and initialized with specified values.
STOR1 DW 100 DUP(0); Reserve an array of 100
words of memory and initialize all words with
0000.Array is named as STOR1.
 END: END directive is placed after the last
statement of a program to tell the assembler that
this is the end of the program module. The
assembler will ignore any statement after an
END directive. Carriage return is required after
the END directive.
ENDP: ENDP directive is used along with the
name of the procedure to indicate the end of a
procedure to the assembler
Example:
SQUARE_NUM PROCE ; It start the procedure;
Some steps to find the square root of a number
SQUARE_NUM ENDP ; Hear it is the End for the
procedure
 PAGE 60,132

EXAMPLE SOURCE PROGRAM

TITLE EXAM1 Move And Add
;----------------------------------------------------------------------------------------------------------------
STACKSG SEGMENT PARA STACK Stack
DW 32 DUP(?)
STACKSG ENDS
;----------------------------------------------------------------------------------------------------------------
DATASG SEGMENT PARA Data
FLDA DW 250
FLDB DW 125
FLDC DW ?
DATASG ENDS
;----------------------------------------------------------------------------------------------------------------
CODESG SEGMENT PRAR Code
BEGIN PROC FAR
ASSUME CS:CODESG, DS:DATASG
SS:STACKSG, EX:NOTHING
PUSH DS
SUB AX,AX
PUSH AX
MOV AX, DATASG
MOV DS,AX
MOV AX, FLDA
ADD AX, FLDB
MOV FLDC, AX
RET
BEGIN ENDP
CODESG ENDS
END BEGIN
 PSEUDO-OPERATIONS(Directives)

Assembler Supports a number of

instructions that enable you to control the
way in which a program assembles and
lists, These instructions, named
---PSEUDO Operations.
EXAMPLE SOURCE PROGRAM
1
PAGE and TITLE
Listing Pseudo-Operations(Listing Directives)
PAGE 60,132
Lines per page: May range from 10 to 255
Characters per Line: May range from 60 to 132
*Omission of a PAGE Statement. Cause the assembler
assume PAGE 66,80
*PAGE with no operand. Force skip to next page.
TITLE Text
You can cause a title form a program to print at the top of
each page using TITLE pseudo-ops.
*text:max up to 60 chars
*SUBTTL .
EXAMPLE SOURCE PROGRAM 2 SEGMENT.ENDS
Memory Pseudo-Operation (Memory Directives)
<Segname> SEGMENT[<align>][<combine>][<class>]
<Segname> ENDS
segname:must be unique, legal name.
must not be a reserved word.
align: maybe:
1.PAGEaddress is XXX00H
2.PARA---address is XXXX0H(Default)
3.WORDaddress is XXXXEH(E:EVEN)
4.BYTE---address is XXXXXH(ANY WHERE)
combine: Maybe:
1.None(not combinable or Private)(Default)
2.PUBLIC
3.STACK
4.COMMON
5.AT <exp>
6.MEMORY
EXAMPLE SOURCE PROGRAM

3
DB, DW, DD, DQ, DT
Memory Pseudo-Operation( Memory Directive)
<varname> DB <exp>[,<exp>,]
<varname> DW <exp>[,<exp>,]
<varname> DD <exp>[,<exp>,]
<varname> DQ <exp>[,<exp>,]
<varname> DT <exp>[,<exp>,]
DB : Define Byte ( allocate ONE BYTE, 8 bits)
DW: Define Word ( allocate ONE WORLD, 16bits)
DD : Define DoubleWord (allocate two words, 32bits)
DQ : Define Quadword ( allocate four words, 64 bits)
DT : Define TenBytes ( allocate ten Bytes, 80 bits)
EXAMPLE SOURCE PROGRAM

3 continue
The directives (Dn) allocate memory in units
specified by the second letter of the directive
(each directive may allocate one or more of its
units at a time)
To define variables
To initial partions of memory
: NUM_BASE DB 16
FILLER DB ?
TABLE DB 10 DUP(A)
BUFFER DB 10 DUP(?)
EXAMPLE SOURCE PROGRAM
4
PROC
Memory Pseudo-Operation (Memory Directive)
<procname> PROC [NEAR] or [FAR]
..
RET
<procname> ENDP
Default is no operand NEAR
Use FAR if:
1. The procedure name is an operating system entry point
2. The procedure will be called from code with has another
ASSUME CS value.
*each proc block should contain a RET.
EXAMPLE SOURCE PROGRAM

5
ASSUME
Memory Pseudo operation (Memory
Directive)
ASSUME <seg-reg>:<seg-name>[,.]
ASSUME tells the assembler that the
sysbols in the segment or group can be
accessed using this segment Register.
EXAMPLE SOURCE PROGRAM

6
END
Memory Pseudo-Operation ( Memory
Directive)
END [<exp>]
*The END statement specifies the end of
the program