8051 Syllabus

8051 Microcontroller: Microcontroller families,

8051 Architecture, Signal Description, Register
organization, Internal RAM, Special Function Registers,
Interrupt control flow, Timer/Counter Operation, Serial
Data Communication, and RS-232C Standard.

8051 Programming & Interfacing: Addressing

modes, Instruction set, Simple Programs involving
Arithmetic and Logical Instructions, Timers/Counters,
Serial Communication & Interrupts.

Interfacing: Matrix Key Board, Stepper Motor, LCDs,

DAC & ADC.
Microcontroller
8051
Contents:
Introduction
Block Diagram and Pin Description of the 8051
Registers
Memory mapping in 8051
Stack in the 8051
I/O Port Programming
Timer
Serial Communication
Interrupt
 Microprocessors:
General-purpose microprocessor
CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example Intels x86, Motorolas 680x0

Many chips on mothers board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port Port
processor

Address Bus

General-Purpose Microprocessor System

 Microcontroller :
A smaller computer
On-chip RAM, ROM, I/O ports...
Example Motorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
CPU is stand-alone, RAM, CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
designer can decide on the fix amount of on-chip ROM,
amount of ROM, RAM and RAM, I/O ports
I/O ports. for applications in which cost,
expensive power and space are critical
versatility single-purpose
general-purpose
 Block Diagram
External interrupts
On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1 Counter
Control program
code RAM Timer 0 Inputs

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data
Pin Description of the 8051
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 8051 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7
(8031) 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
Pins of 8051 1/4

Vcc pin 40
Vcc provides supply voltage to the chip.
The voltage source is +5V.
GND pin 20 ground
XTAL1 and XTAL2 pins 19,18
 Figure (a). XTAL Connection to 8051

Using a quartz crystal oscillator

We can observe the frequency on the XTAL2 pin.

C2
XTAL2
30pF

C1
XTAL1
30pF

GND
 Pins of 8051 2/4

RST pin 9 reset

It is an input pin and is active high normally low .
The high pulse must be high at least 2 machine
cycles.
It is a power-on reset.
Upon applying a high pulse to RST, the
microcontroller will reset and all values in registers
will be lost.
Reset values of some 8051 registers
Figure (b). Power-On RESET Circuit
Vcc

10 uF 31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST
Pins of 8051 3/4

/EA pin 31 external access

There is no on-chip ROM in 8031 and 8032 .
The /EA pin is connected to GND to indicate the code is
stored externally.
/PSEN ALE are used for external ROM.
For 8051, /EA pin is connected to Vcc.
/ means active low.
/PSEN pin 29 program store enable
This is an output pin and is connected to the OE pin of the
ROM.
 Pins of 8051 4/4
ALE pin 30 address latch enable
It is an output pin and is active high.
8051 port 0 provides both address and data.
The ALE pin is used for de-multiplexing the address and data
by connecting to the G pin of the 74LS373 latch.
I/O port pins
The four ports P0, P1, P2, and P3.
Each port uses 8 pins.
All I/O pins are bi-directional.
 Pins of I/O Port

The 8051 has four I/O ports

Port 0 pins 32-39 P0 P0.0 P0.7
Port 1 pins 1-8 P1 P1.0 P1.7
Port 2 pins 21-28 P2 P2.0 P2.7
Port 3 pins 10-17 P3 P3.0 P3.7
Each port has 8 pins.
Named P0.X X=0,1,...,7 , P1.X, P2.X, P3.X
Ex P0.0 is the bit 0 LSB of P0
Ex P0.7 is the bit 7 MSB of P0
These 8 bits form a byte.
Each port can be used as input or output (bi-direction).
Other Pins
P1, P2, and P3 have internal pull-up resisters.
P1, P2, and P3 are not open drain.
P0 has no internal pull-up resistors and does not
connects to Vcc inside the 8051.
P0 is open drain.
Compare the figures of P1.X and P0.X.
However, for a programmer, it is the same to program
P0, P1, P2 and P3.
All the ports upon RESET are configured as output.
Port 0 with Pull-Up Resistors

Vcc
10 K

P0.0
DS5000 P0.1

Port 0
P0.2
8751 P0.3
8951 P0.4
P0.5
P0.6
P0.7
Port 3 Alternate Functions
P3 Bit Function Pin

P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17
RESET Value of Some 8051 Registers:

Register Reset Value

PC 0000
ACC 00
B 00
PSW 00
SP 07
DPTR 0000
RAM are all zero.
 Registers
A

R0
DPH DPL DPTR
R1

R2
PC PC

R3

Some 8051 16-bit Register

R4

R5

R6

R7

Some 8-bit Registers of the

8051
RAM memory space allocation in the 8051

7FH

Scratch pad RAM

30H
2FH
Bit-Addressable RAM

20H
1FH Register Bank 3

18H
17H Register Bank 2

10H
0FH Register Bank 1( Stack)

08H
07H Register Bank 0
00H
8051 Flag bits and the PSW register

CY AC F0 RS1 RS0 OV -- P

Carry flag PSW.7CY

Auxiliary carry flag PSW.6AC
Available to the user for general purpose PSW.5--
Register Bank selector bit 1 PSW.4RS1
Register Bank selector bit 0 PSW.3RS0
Overflow flag PSW.2OV
User define bit PSW.1--
Parity flag Set/Reset odd/even parity PSW.0P

RS1 RS0 Register Bank Address

0 0 0 00H-07H

0 1 1 08H-0FH

1 0 2 10H-17H

1 1 3 18H-1FH
Addressing Modes
Immediate
Register
Direct
Register Indirect
Indexed
Immediate Addressing Mode
MOV A,#65H

MOV A,#A

MOV R6,#65H

MOV DPTR,#2343H

MOV P1,#65H
Register Addressing Mode
MOV Rn, A ;n=0,..,7
ADD A, Rn
MOV DPL, R6

MOV DPTR, A
MOV Rm, Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be acces sed using direct addressing mode, it is most often used to acce ss RAM loc. 30 7FH.

MOV R0, 40H

MOV 56H, A
MOV A, 4; MOV A, R4
MOV 6, 2 ; copy R2 to R6
; MOV R6,R2 is invalid !

S FR re gister and their address

MOV 0E0H, #66H ; MOV A,#66H

MOV 0F0H, R2 ; MOV B, R2
MOV 80H,A ; MOV P1,A
Register Indirect Addressing Mode
In this mode, register is used as a pointer to the data.

MOV A,@Ri ; move content of RAM loc. Where address is held by Ri into A
( i=0 or 1 )
MOV @R1,B

In other word, th e conten t of register R0 or R1 is sources or target in MOV, ADD and SUBB in structions.
Example: Write a program to copy a block of 10 b ytes from RAM location starting at 40H to RAM location starting at 60H.
Solution:
MOV R0,#40H ; source pointer
MOV R1,#60H ; destination pointer
MOV R2,#10 ; counter
B ACK: MOV A,@R0
MOV @R1,A
INC R0
INC R1
DJNZ R2,BACK
Indexed Addressing Mode And On-Chip ROM Access
This mode is widely used in accessing data elements of look-up table entries located in the program (code) space ROM at the 8051

MOVC A,@A+DPTR
A= content of address A +DPTR from ROM
Note:
Because the data elements are stored in the program (code ) space ROM of the 8051, it uses the instruction MOVC instead of MOV. The C means code.
SJMP and LJMP:

LJMP(long jump)
LJMP is an unconditional jump. It is a 3-byte instruction in which the first byte is the op-code, and the second and third bytes represent the 16-bit address of the target location. The 20byte target address allows a jump to any memory location
from 0000 to FFFFH.

SJMP(short jump)
In this 2-byte instruction. The first byte is the op-code and the second byte is the relative address of the target location. The relative address range of 00-FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of
memory relative to the address of the current PC.
MUL & DIV
MUL AB ;B|A = A*B
MOV A,#25H
MOV B,#65H
MUL AB ;25H*65H=0E99
;B=0EH, A=99H
DIV AB ;A = A/B, B = A mod B
MOV A,#25H
MOV B,#10H
DIV AB ;A=2, B=5
Rotate
EXAMPLE:

RR:

RRC:

RL:

RLC:

C
 ACALL: Absolute Call JC: Jump if Carry Set PUSH: Push Value Onto Stack

ADD, ADDC: Add Acc. (With Carry) JMP: Jump to Address RET: Return From Subroutine

AJMP: Absolute Jump JNB: Jump if Bit Not Set RETI: Return From Interrupt

ANL: Bitwise AND JNC: Jump if Carry Not Set RL: Rotate Accumulator Left

CJNE: Compare & Jump if Not Equal JNZ: Jump if Acc. Not Zero RLC: Rotate Acc. Left Through Carry

CLR: Clear Register JZ: Jump if Accumulator Zero RR: Rotate Accumulator Right

CPL: Complement Register

8051 INSTRUCTION SET LCALL: Long Call RRC: Rotate Acc. Right Through Carry

DA: Decimal Adjust LJMP: Long Jump SETB: Set Bit

DEC: Decrement Register MOV: Move Memory SJMP: Short Jump

DIV: Divide Accumulator by B MOVC: Move Code Memory SUBB: Sub. From Acc. With Borrow

DJNZ: Dec. Reg. & Jump if Not Zero MOVX: Move Extended Memory SWAP: Swap Accumulator Nibbles

INC: Increment Register MUL: Multiply Accumulator by B XCH: Exchange Bytes

JB: Jump if Bit Set NOP: No Operation XCHD: Exchange Digits

JBC: Jump if Bit Set and Clear Bit ORL: Bitwise OR XRL: Bitwise Exclusive OR

POP: Pop Value From Stack Undefined: Undefined Instruction

 ADD A,Rn
Arithmetic instructions:
SUBB A, Direct
ADD A,Direct SUBB A,@Ri
ADD A,@Ri SUBB A,#Data
ADD A,#Data INC A
ADDC A,Rn INC Rn
ADDC A, Direct INC Direct
ADDC A,@Ri INC @Ri
ADDC A,@Data DEC A
SUBB A,Rn DEC Rn
 DEC Direct
Arithmetic instructions:

DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
 ANL A,Rn
Logical instructions:
ORL A,#Data
ANL A,Direct ORL Direct,A
ANL A,@Ri ORL Direct,#Data
ANL A,#Data XRL A,Rn
ANL Direct,A XRL A,Direct
ANL Direct,#Data XRL A,@Ri
ORL A,Rn XRL A,#Data
ORL A,Direct XRL Direct,A
ORL A,@Ri XRL Direct,#Data
 CLR A
Logical instructions:

CPL A
RL A
RLC A
RR A
RRC A
SWAP A
 MOV A,Rn
Data transfer instructions:
MOV Direct, Direct
MOV A, Direct MOV Direct,@Ri
MOV A,@Ri MOV Direct,#Data
MOV A,#Data MOV @Ri,A
MOV Rn,A MOV @Ri,Direct
MOV Rn,Direct MOV @Ri,#Data
MOV Rn,#Data MOV DPTR,#Data16
MOV Direct,A MOVX A,@Ri
MOV Direct, Rn MOVX A,@DPTR
 PUSH Direct
Data transfer instructions:

POP Direct
XCH A,Rn
XCH A, Direct
XCH A,@Ri
XCHD A,@Ri
MOVX @Ri,A
MOV @DPTR,A
 CLR C
Boolean Variable Manipulation instructions:
ORL C,/bit
CLR bit MOV C,bit
SETB C MOV bit,C
SETB bit JC rel
CPL C JNC rel
CPL bit JB bit,rel
ANL C,bit JNB bit,rel
ANL C,/bit JBC bit,rel
ORL C,bit
 ACALL addr11
Program branching instructions:
JNZ rel
LCALL addr16 CJNE A,direct,rel
RET CJNE A,#data,rel
RETI CJNE Rn,#data,rel
AJMP addr11 CJNE @Ri,#data,rel
LJMP addr16 DJNZ Rn,rel
SJMP rel DJNZ direct,rel
JMP @A+DPTR NOP
JZ rel
 TIMERS
The 8051 has two timers:
1. TIMER 0
2. TIMER 1

TIMER 0

TIMER 1
 TMOD
Register

Gate : When set, timer only runs while INT(0,1)

is high.
C/T : Counter/Timer select bit.
M1 : Mode bit 1.
M0 : Mode bit 0.
4/4/17
TCON Register (BIT ADRESSABLE
REG)

TCON.7 - TF1: Timer 1 overflow flag.

TCON.6 - TR1: Timer 1 run control bit.
TCON.5 - TF0: Timer 0 overflag.
TCON.4 - TR0: Timer 0 run control bit.
TCON.3 - IE1: External interrupt 1 edge flag.
TCON.2 - IT1: External interrupt 1 type flag.
TCON.1 - IE0: External interrupt 0 edge flag.
TCON.0 - IT0: External interrupt 0 type flag.
Interrupts
 Concept behind Interrupt
An interrupt is an external or internal event that
interrupts the microcontroller to inform it that a device
needs its service
Upon activation of an interrupt, the
microcontroller goes through the following steps
1. It finishes the instruction it is executing and saves
the address of the next instruction (PC) on the stack
2. It also saves the current status of all the interrupts
internally (i.e.: not on the stack)
3. It jumps to a fixed location in memory, called the
interrupt vector table, that holds the address of the ISR
4. The microcontroller gets the address of the ISR from
the interrupt vector table and jumps to it
5. Upon executing the RETI instruction, the
microcontroller returns to the place where it was
TCON REGISTER