DYNAMIC LOGIC

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

EE415 VLSI Design
 Dynamic CMOS
In static circuits the output is connected to
either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type)
devices

Dynamic circuits use temporary storage of

signal values on the capacitance of high
impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type)
transistors

EE415 VLSI Design

 Dynamic Gate
off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)
EE415 VLSI Design
 Conditions on Output
Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.

Inputs to the gate can make at most one

transition during evaluation.

Output can be in the high impedance state

during and after evaluation (PDN off), state is
stored on CL

EE415 VLSI Design

 Properties of Dynamic
Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect
the logic levels
Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (C out)
no Isc, so all the current provided by PDN goes into discharging C L

EE415 VLSI Design

Properties of Dynamic Gates
Overall power dissipation usually higher than static
CMOS
no static current path ever exists between VDD and GND
(including Psc)
no glitching
higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn
low noise margin (NML)
Needs a precharge/evaluate clock
EE415 VLSI Design
 Issues in Dynamic Design
1: Charge Leakage
CLK
Clk Mp
Out

A CL

VOut Evaluate
Clk Me
Precharge

Leakage sources

Leakage is dominated by the subthreshold current

EE415 VLSI Design
 Solution to Charge
Leakage
Keeper

Clk Mp Mkp

A Out
CL
B

Clk Me

Same approach as level restorer for pass-transistor logic

EE415 VLSI Design

 Issues in Dynamic Design
2: Charge Sharing

Charge stored originally on

Clk Mp CL is redistributed (shared)
Out
over CL and CA leading to
A CL reduced robustness
B=0 CA

Clk Me CB

EE415 VLSI Design

 Charge Sharing Example
Clk
Out
A A CL=50fF

Ca=15fF B B B !B Cb=15fF

Cc=15fF C C Cd=10fF

Clk

EE415 VLSI Design

 Charge Sharing
VDD Assume that initial voltage Vx=0 and Vout=VDD
VDD case 1) if V out < VTn Vx increases up to VDD-VTn
Clk Mp
when Ca is small comparing
Mp Out C V = C V t + C V V V
L DD L out a DD Tn X
Out
CL or
A Ma CL Ca
A Ma V out = Vout t V DD = -------- V DD V Tn V X
CL
X X
C
Caa
M
B 0 B = 0 Mb b case 2) if V out > VTn Vx increases less up to
Ca VOUT
Cb ---------------------
-
Vout = V DD when Ca is larger
Me C + CL
Cb a
Clk Me
as CL VDD=CL VOUT + Ca VOUT

EE415 VLSI Design

VOUT = VDD CL / (CL+Ca)
 Solution to Charge
Redistribution
Clk Mp Mkp Clk
Out
A

Clk Me

Precharge internal nodes using a clock-driven transistor

(at the cost of increased area and power)

EE415 VLSI Design

 Issues in Dynamic Design
3: Backgate Coupling
Clk Mp Out1 =1
Out2
A=0 CL1 CL2
In
B=0

Clk Me

Dynamic NAND Static NAND

When In goes up from 0 to VDD, output of
static NAND gate (Out2) goes down from VDD
to 0 and pulls down Out1 through the
capacitive
EE415 VLSI Design coupling
 Backgate Coupling Effect

Out1
Voltage

Clk

In Out2

Time, ns

EE415 VLSI Design

 Issues in Dynamic Design
4: Clock Feed Through

Coupling between Out and Clk

Clk Mp input of the precharge device due
Out to the gate to drain capacitance.
A CL

B So voltage of Out can rise above

VDD.
Clk Me

The fast rising (and falling edges)

of the clock couple to Out.

EE415 VLSI Design

 Clock Feed Through
Clock feed through
Clk
Out
In1
In2 Voltage

In3 In &
Clk
In4 Out
Clk
Time, ns
Clock feed through
More noise is generated as
EE415 VLSI Design
a result of clock coupling
 Other Effects

Capacitive coupling between output

wires pulls down prestored charges
Substrate coupling
Minority charge injection
Supply noise (negative ground bounce

may discharge the output)

EE415 VLSI Design

 Cascading Dynamic Gates
V

Clk
Clk Clk
Mp Mp
Out2 In Output signal loss
Out1
In VTn
Out1
Clk Me Clk Me
V
Out2

Only 0 1 transitions allowed at inputs!

So do not connect these gates directly
EE415 VLSI Design
 Domino Logic

Clk Mp Clk Mp Mkp

11 Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5

Clk Me Clk Me

Here we guarantee proper 0 to 1 transitions

between gates
EE415 VLSI Design
 Why Domino?

Clk

Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk

Like falling dominos!

EE415 VLSI Design
Properties of Domino Logic

Only non-inverting logic can be implemented

Very high speed
static inverter can be skewed, only L-H transition
so make PMOS of inverter stronger
Input capacitance reduced
so smaller logical effort

EE415 VLSI Design

 Designing with Domino
Logic
VDD VDD
VDD

Clk Mp Clk Mp Mr
Out1

Out2
In1
In2 PDN In4 PDN
In3
Can be eliminated!
but be aware of the
Clk Me Clk Me short circuit path from
delayed clock
Inputs = 0
during precharge
EE415 VLSI Design
 Footless Domino
VDD VDD VDD

Clk Mp Clk Mp Clk Mp

Out1 Out2 Outn
0 1 0 1 0 1
In1 In2 In3 Inn
1 0 1 0

The first gate in the chain needs a foot switch

Precharge is rippling short-circuit current
A solution is to delay the clock for each stage
EE415 VLSI Design
 Differential (Dual Rail)
Domino
off on
Clk Mp Mkp Mkp Mp Clk
Out = AB Out = AB
1 0 1 0
A
!A !B
B

Clk Me

Solves the problem of non-inverting logic

EE415 VLSI Design

 np-CMOS

Mp Clk Me Possible coupling

Clk
11 Out1 in longer runs to
10 dynamic node
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
Mp
(to PDN)
Clk Me Clk

Only 0 1 transitions allowed at inputs of PDN

Only 1 0 transitions allowed at inputs of PUN
EE415 VLSI Design
 NORA Logic
Clk Me use np-CMOS blocks
Clk Mp
11 Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp

to other to other
PDNs PUNs

WARNING: Very sensitive to noise!

EE415 VLSI Design