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# Low-Power Design and

Test

## Dynamic and Static Power in

Vishwani D. Agrawal Srivaths Ravi
CMOS
Auburn University, USA Texas Instruments India
vagrawal@eng.auburn.edu Srivaths.ravi@ti.com

## Hyderabad, July 30-31, 2007

http://www.eng.auburn.edu/~vagrawal/hyd.html

## Copyright Agrawal & Srivaths, 2 Low-Power Design and Test, Lecture 2 1

007
Components of Power
Dynamic
Signal
transitions
Logic activity
Glitches
Short-circuit
Ptotal = Pdyn + Pstat
Static
Leakage Ptran + Psc + Pstat

## Copyright Agrawal & Low-Power Design and Test 2

Srivaths, 2007 , Lecture 2
Power of a Transition: Ptran

VDD
Ron
ic(t)
vi (t) vo(t)

R = large CL

Ground

## Copyright Agrawal & Low-Power Design and Test 3

Srivaths, 2007 , Lecture 2
Charging of a Capacitor
R

t=0
i(t) v(t)
V C

## Copyright Agrawal & Low-Power Design and Test 4

Srivaths, 2007 , Lecture 2
i(t) = C dv(t)/dt = [V v(t)] /R
dv(t) V v(t)
=
dt RC
dv(t) dt
=
V v(t) RC
-t
ln [V v(t)] = + A
RC
Initial condition, t = 0, v(t) = 0 A = ln V
-t
v(t) = V [1
exp()]
Copyright Agrawal & Low-Power Design and Test
RC 5
Srivaths, 2007 , Lecture 2
-t
v(t) = V [1 exp( )]
RC

dv(t) V -t
i(t) = C = exp( )
dt R RC

## Copyright Agrawal & Low-Power Design and Test 6

Srivaths, 2007 , Lecture 2
Total Energy Per Charging
Transition from Power Supply

V2 -t
Etrans = V i(t) dt = exp( ) dt
0 0 R RC
= CV2

## Copyright Agrawal & Low-Power Design and Test 7

Srivaths, 2007 , Lecture 2
Energy Dissipated per Transition
in Resistance

2 V2 -2t
R i (t) dt = R exp( ) dt
0 R 0
2
RC

1
= CV2
2

## Copyright Agrawal & Low-Power Design and Test 8

Srivaths, 2007 , Lecture 2
Energy Stored in Charged
Capacitor

-t V -t
v(t) i(t) dt = V [1-exp( )] exp( )
dt
0 0 RC R RC
1
= CV2
2

## Copyright Agrawal & Low-Power Design and Test 9

Srivaths, 2007 , Lecture 2
Transition Power
Gate output rising transition
Energy dissipated in pMOS transistor = CV 2/2
Energy stored in capacitor = CV 2/2
Gate output falling transition
Energy dissipated in nMOS transistor = CV 2/2
Energy dissipated per transition = CV 2/2
Power dissipation:

## Ptrans = Etrans fck = fck CV2/2

= activity factor
Copyright Agrawal & Low-Power Design and Test 10
Srivaths, 2007 , Lecture 2
Components of Power
Dynamic
Signal
transitions
Logic activity
Glitches
Short-circuit
Ptotal = Pdyn + Pstat
Static
Leakage Ptran + Psc + Pstat

## Copyright Agrawal & Low-Power Design and Test 11

Srivaths, 2007 , Lecture 2
Short Circuit Power of a
Transition: Psc

VDD

isc(t)
vi (t) vo(t)

CL

Ground

## Copyright Agrawal & Low-Power Design and Test 12

Srivaths, 2007 , Lecture 2
Short Circuit Current, isc(t)
VDD
VDD - VTp n-transistor
Vi (t)
cuts-of
Volt Vo(t)

VTn
p- 0
transistor Iscmaxf
starts
conducting
isc(t)
Isc

Time (ns)
0 tB tE 1

## Copyright Agrawal & Low-Power Design and Test 13

Srivaths, 2007 , Lecture 2
Peak Short Circuit Current
Increases with the size (or gain, ) of
transistors
Decreases with load capacitance, CL
Largest when CL = 0
Reference: M. A. Ortega and J. Figueras,
Short Circuit Power Modeling in
Submicron CMOS, PATMOS 96, Aug.
1996, pp. 147-166.

## Copyright Agrawal & Low-Power Design and Test 14

Srivaths, 2007 , Lecture 2
Short-Circuit Energy per
Transition
Escf = tBtE VDD isc(t)dt

## Escf = Escr = 0, when VDD = |VTp| + VTn

Copyright Agrawal & Low-Power Design and Test 15
Srivaths, 2007 , Lecture 2
Short-Circuit Energy
Increases with rise and fall times of
input
Decreases for larger output load
capacitance
Decreases and eventually becomes
zero when VDD is scaled down but the
threshold voltages are not scaled
down
Copyright Agrawal & Low-Power Design and Test 16
Srivaths, 2007 , Lecture 2
Short-Circuit Power
Calculation
Assume equal rise and fall times
Model input-output capacitive coupling
(Miller capacitance)
Use a spice model for transistors
T. Sakurai and A. Newton, Alpha-power
Law MOSFET model and Its Application to
a CMOS Inverter, IEEE J. Solid State
Circuits, vol. 25, April 1990, pp. 584-594.

## Copyright Agrawal & Low-Power Design and Test 17

Srivaths, 2007 , Lecture 2
Short Circuit Power

## Copyright Agrawal & Low-Power Design and Test 18

Srivaths, 2007 , Lecture 2
Psc, Rise Time and
Capacitance
VDD
VDD
Ron
ic(t)+isc(t)
vi (t) vo(t)
vo(t)

CL tr
tf R = large
vo(t)
Ground
R

## Copyright Agrawal & Low-Power Design and Test 19

Srivaths, 2007 , Lecture 2
isc, Rise Time and
Capacitance

-t
VDD[1- exp()]
vo(t) R(t) C
Isc(t) = =
R(t) R(t)

## Copyright Agrawal & Low-Power Design and Test 20

Srivaths, 2007 , Lecture 2
iscmax, Rise Time and Capacitance

i
Small C Large C
vo(t) vo(t)
iscmax 1

R(t)

t
tf
Copyright Agrawal & Low-Power Design and Test 21
Srivaths, 2007 , Lecture 2
Psc, Rise Times, Capacitance
For given input rise and fall times
short circuit power decreases as
output capacitance increases.
Short circuit power increases with
increase of input rise and fall times.
Short circuit power is reduced if
output rise and fall times are smaller
than the input rise and fall times.

## Copyright Agrawal & Low-Power Design and Test 22

Srivaths, 2007 , Lecture 2
Summary: Short-Circuit
Power
Short-circuit power is consumed by each
transition (increases with input transition
time).
Reduction requires that gate output transition
should not be faster than the input transition
(faster gates can consume more short-circuit
power).
Increasing the output load capacitance
reduces short-circuit power.
Scaling down of supply voltage with respect to
threshold voltages reduces short-circuit power;
completely eliminated when VDD |Vtp|+Vtn .

## Copyright Agrawal & Low-Power Design and Test 23

Srivaths, 2007 , Lecture 2
Components of Power

Dynamic
Signal transitions
Logic activity
Glitches
Short-circuit
Static
Leakage

## Copyright Agrawal & Low-Power Design and Test 24

Srivaths, 2007 , Lecture 2
Leakage Power
VDD
Ground IG
Gate
R
Source Drain
n+ Isub n+
IPT
Bulk Si (p) IGIDL ID

nMOS Transistor

## Copyright Agrawal & Low-Power Design and Test 25

Srivaths, 2007 , Lecture 2
Leakage Current Components
Subthreshold conduction, Isub
Reverse bias pn junction conduction, ID
Gate induced drain leakage, IGIDL due to
tunneling at the gate-drain overlap
Drain source punchthrough, IPT due to
short channel and high drain-source
voltage
Gate tunneling, IG through thin oxide;
may become significant with scaling
Copyright Agrawal & Low-Power Design and Test 26
Srivaths, 2007 , Lecture 2
Subthreshold Current

## 0: carrier surface mobility

Cox: gate oxide capacitance per unit area
L: channel length
W: gate width
Vt = kT/q: thermal voltage
n: a technology parameter
Copyright Agrawal & Low-Power Design and Test 27
Srivaths, 2007 , Lecture 2
IDS for Short Channel Device

## VDS = drain to source voltage

: a proportionality factor

## W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submic

Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp. 81-104

## Copyright Agrawal & Low-Power Design and Test 28

Srivaths, 2007 , Lecture 2
Increased Subthreshold Leakage

Scaled device
Ic
Log (Drain current)

Isub

## 0 VTH VTH Gate voltage

Copyright Agrawal & Low-Power Design and Test 29
Srivaths, 2007 , Lecture 2
Summary: Leakage Power
Leakage power as a fraction of the total power
increases as clock frequency drops. Turning
supply of in unused parts can save power.
For a gate it is a small fraction of the total
power; it can be significant for very large
circuits.
Scaling down features requires lowering the
threshold voltage, which increases leakage
power; roughly doubles with each shrinking.
Multiple-threshold devices are used to reduce
leakage power.

## Copyright Agrawal & Low-Power Design and Test 30

Srivaths, 2007 , Lecture 2
Technology Scaling
Scaling down 0.7 micron by factors 2
and 4 leads to 0.35 and 0.17 micron
technologies
Constant electric field assumed

## Copyright Agrawal & Low-Power Design and Test 31

Srivaths, 2007 , Lecture 2
Constant Electric Field
Scaling
B. Davari, R. H. Dennard and G. G.
Shahidi, CMOS Scaling for High
Performance and Low PowerThe
Next Ten Years, Proc. IEEE, April
1995, pp. 595-606.
Other forms of scaling are referred to
as constant-voltage and quasi-
constant-voltage.

## Copyright Agrawal & Low-Power Design and Test 32

Srivaths, 2007 , Lecture 2
Bulk nMOSFET

Polysilicon

Gate
Drain
Source W
n+ n+
L
p-type body (bulk)

SiO2
Thickness = tox

## Copyright Agrawal & Low-Power Design and Test 33

Srivaths, 2007 , Lecture 2
Technology Scaling
A scaling factor (S ) reduces device dimensions
as 1/S.
Successive generations of technology have used
a scaling S = 2, doubling the number of
transistors per unit area. This produced 0.25 ,
0.18, 0.13, 90nm and 65nm technologies,
continuing on to 45nm and 30nm.
A 5% gate shrink (S = 1.05) is commonly applied
to boost speed as the process matures.

## N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Bosto

Pearson Addison-Wesley, 2005, Section 4.9.1.

## Copyright Agrawal & Low-Power Design and Test 34

Srivaths, 2007 , Lecture 2
Constant Electric Field
Scaling
Device Parameter Scaling
Length, L 1/S
Width, W 1/S
Gate oxide thickness, tox 1/S
Supply voltage, VDD 1/S
Threshold voltages, Vtn, Vtp 1/S
Substrate doping, NA S

## Copyright Agrawal & Low-Power Design and Test 35

Srivaths, 2007 , Lecture 2
Constant Electric Field Scaling
(Cont.) Scalin
Device Characteristic
g
W / (L tox) S
Current, Ids (VDD Vt ) 2 1/S
Resistance, R VDD / Ids 1
Gate capacitance, C W L / tox 1/S
Gate delay, RC 1/S
Clock frequency, f 1/ S
Dynamic power per gate, P CV 2 f 1/S 2
Chip area, A 1/S 2
Power density P/A 1
Current density Ids /A S
Copyright Agrawal & Low-Power Design and Test 36
Srivaths, 2007 , Lecture 2
Problem: A Design Example
A battery-operated 65nm digital CMOS device is
found to consume equal amounts (P ) of dynamic
power and leakage power while the short-circuit
power is negligible. The energy consumed by a
computing task, that takes T seconds, is 2PT.
Compare two power reduction strategies for
extending the battery life:
A. Clock frequency is reduced to half, keeping all other
parameters constant.
B. Supply voltage is reduced to half. This slows the gates
down and forces the clock frequency to be lowered to
half of its original (full voltage) value. Assume that
leakage current is held unchanged by modifying the
design of transistors.

## Copyright Agrawal & Low-Power Design and Test 37

Srivaths, 2007 , Lecture 2
Solution: Part A. Clock
Frequency Reduction
Reducing the clock frequency will reduce
dynamic power to P / 2, keep the static
power the same as P, and double the
execution time of the task.
Energy consumption for the task will be,
Energy = (P / 2 + P ) 2T = 3PT
which is greater than the original 2PT.

## Copyright Agrawal & Low-Power Design and Test 38

Srivaths, 2007 , Lecture 2
Solution: Part B. Supply Voltage
Reduction
When the supply voltage and clock frequency
are reduced to half their values, dynamic
power is reduced to P / 8 and static power to
P / 2. The time of task is doubled and the total
energy consumption is,
Energy = (P / 8 + P / 2) 2T = 5PT / 4 =1.25PT
The voltage reduction strategy reduces
energy consumption while a simple frequency
reduction consumes more energy.

## Copyright Agrawal & Low-Power Design and Test 39

Srivaths, 2007 , Lecture 2