Logic Gates

Logic gates are electronic digital circuit

perform logic functions. Commonly
expected logic functions are already
having the corresponding logic circuits
in Integrated Circuit (I.C.) form.
Design of Circuit
Procedures
1. Obtain a precise circuit specification
2. Development of a truth table
3. Identifying the minterms
corresponding to each row in the table.
4. Drawing Karnaugh maps
5. Forming groups of 1's on the Karnough map
6. Writing the reduced expression
7. Converting the reduced expression into a real
izable expression
8. Drawing the circuit diagram
9. Construct and test a prototype circuit.
Types of Logic Gates
A N D G a te N A N D G a te
A A
C C
B B
O R G a te N O R G a te
A A
C C
B B
N O T G a te E x c lu s iv e - O R G a t e
A
A C A B=C
B
Basic Gates

AND , OR , NOT
AND Gate
The AND gate implements the Boolean AND
function where the output only is logical 1
when all inputs are logical 1.
The standard symbol and the truth tabel for a
two input AND gate is:
Boolean expression of AND
The Boolean expression for the
AND gate is R=A.B

A B R
0 0 0
0 1 0
1 0 0
1 1 1
OR Gate
The OR gate implements the Boolean
OR function where the output is logical
1 when just input is logical 1.
The standard symbol and the truth table
for a two input OR gate is:
Boolean Expression of OR
The Boolean expression for
the OR gate is: R=A+B
A B R
0 0 0
0 1 1
1 0 1
1 1 1
NOT Gate
The NOT gate implements the
Boolean NOT function where the
output is the inverse of the input.
The standard symbol and the truth
table for the NOT gate is:
Boolean Expression of NOT
The Boolean expression for the
NOT gate is: R=-A

A R

0 1

0 0
Derived Gates

NAND , NOR , XOR

NAND Gate
The NAND gate is an AND gate followed by a
NOT gate. The output is logical 1 when one of
the inputs are logical 0
The standard symbol and the truth table for
the NAND gate is:
Boolean expression of
NAND

A B R
0 0 1
0 1 1
1 0 1
1 1 0
NOR Gate
The NOR is a combination of an OR followed by
a NOT gate. The output is logical 1 when non
of the inputs are logical 0
The standard symbol and the truth table for
the NOR gate is:
Boolean Expression of
NOR

A B R
0 0 1
0 1 0
1 0 0
1 1 0
XOR Gate
The XOR gate produces a logic 1 output only
if its two inputs are different. If the inputs
are the same, the output is a logic 0
The XOR symbol is a variation on the
standard OR symbol. It consists of a plus (+)
sign with a circle around it. The logic
symbol, as shown here, is a variation on the
standard OR symbol.
Exercise 1

http://kom.auc.dk/logic/
 De-Morgans Theorem and
Logic Conversion
1) ( A B) A B A
= A
C
B B

2) ( A B ) A B A
= A
C
B B

3) A B A B A B A A
B = B C

A A
4) A B A B A B B = B C
Implement the logic expression
using NAND gates only
1) Z X Y Z
X
X Y Z Y
Z
X Y Z

X Y Z
X
2) Z XY XZ YZ Y

X
XY XZ YZ Z

Y XY +XZ + YZ
XY XZ YZ Z
 Implement logic expression
using NOR gates only
1) Z (X Y) (X Y)
(X Y) (X Y)
X Y X Y

X
Y W
Revision Exercise
http://www.nottingham.ac.uk/~
cczwood/TestCourses
/logic/logic-intro.html
http://www.cs.odu.edu/~jbollen
/CS149/demos.html
http://sandbox.mc.edu/~bennet
/cs110/boolalg/gate.html
http://www.cs.stedwards.edu/~
jsnowde/start.htm
Combinational Logic
Designs
A combinational logic circuit can be described by
the block schematic shown
I1 O1
: Combinational :
: Logic :
In On
Each output is a function of some or all of the
input variables, Hence
O1=f(I1,I2,....,In) O2=f(I1,I2,,In) ...
and On=f(I1,I2,,In)
Half Adder
What is a Half adder?
Logic gate that perform addition
for 1-bit
When 1 + 1 occurs, a carry
produce 1
 Half Adder
Perform arithmetic additions
two inputs A, B to half-adder. Resultants are
Sum(S) and Carry(Cout)
A S
H.A
B Cout
Using K-Map to simplify the sum term, we get
A B S C
0 0 0 0
S A B AB A S
B 0 1 1 0
A B 1 0 1 0
Cout
C AB 1 1 0 1
Full Adder
What is Full Adder?
A full adder is a circuit that computes the
sum of three bits and gives a two-bit answer.
A circuit for adding two 16-bit numbers can
be built from 16 full-adder circuits. Each full-
adder does one column of the sum.
The full adder for a given column adds two
bits from the input numbers together with a
one-bit carry from the previous column to the
right. The adder produces a two-bit answer;
one of these bits is used as a carry into the
next column.
 A
B
F u ll S
Adder C out
Full Adder C in

A full adder has 3 inputs and 2 outputs

The truth table of the full-adder can be
drawn with inputs A,B and Cin with outputs S and Cout
From the truth table we can write the Boolean equation
for the S and Cout
S A B Cin A BC in AB C in ABCin
Cout A BCin AB Cin ABC in ABCin
Simplify using Boolean Algebra and K-map, we get

S A B Cin
Cout ACin BCin AB
Sum = Any 2 of the three inputs are
1
Cout = XOR between A, B, Cin
A B Cin Sum Cout
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Full Adder diagram
Half Subtractor
What is a Half Subtractor
A logic gate that perform 1 bit
subtraction
When 0-1 occurs, a carry produces
1
Half Subtractor

A0 B0 D0 C 1 A0
D0
0 0 0 0 B0
0 1 1 1
1 0 1 0
C1
1 1 0 0
1 2
0
-1
1
Half Subtractor
Operation: A - B A
D
H S
B Bout
D A B AB
A B D Bout
Bout A B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Full Subtractor
What is a Full Subtraction?
Logic gates that perform two bits
subtraction
Full Subtractor
Ci Ai Bi Di Ci+1 AiBi
Ci 00 01 11 10
0 0 0 0 0
0 0 1 1 1 0 1 1
0 1 0 1 0
1 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
Di
1 1 0 0 0
1 1 1 1 1 Di = Ci $ (Ai $ Bi)

Same as Si in full adder

Full Subtractor
AiBi
Ci Ai Bi Di Ci+1 Ci 00 01 11 10
0 0 0 0 0 0 1
0 0 1 1 1
0 1 0 1 0 1 1 1 1
0 1 1 0 0
1 0 0 1 1 Ci+1
1 0 1 0 1
1 1 0 0 0 Ci+1 = !Ai & Bi
1 1 1 1 1 # Ci & !Ai & !Bi
# Ci & Ai & B i
Full Subtractor
Ci+1 = !Ai & Bi
# Ci & !Ai & !Bi
# Ci & Ai & Bi

Ci+1 = !Ai & Bi

# Ci & (!Ai & !Bi # Ai & Bi)

Ci+1 = !Ai & Bi # Ci & !(Ai $ Bi)

Recall:
Di = Ci $ (Ai $ Bi)
Ci+1 = !Ai & Bi # Ci & !(Ai $ Bi)
Full Subtractor
Di = Ci $ (Ai $ Bi)
Ci+1 = !Ai & Bi # Ci & !(Ai $ Bi)
Ci

Ai Di
Bi

C i+1
half subtractor
half subtractor
Full Subtractor
A B Bin D Bout
Operation: A - B - Bin
0 0 0 0 0

D A B Bin A BB in ABBin AB B in 0 0 1 1 1

Bout A Bin A B BBin 0 1 0 1 1

0 1 1 0 1
A
D 1 0 0 1 0
B F S
Bout 1 0 1 0 0
B in
1 1 0 0 0
1 1 1 1 1
 Adder/Subtractor - 1
A0 A0
S0 D0
B0 B0

C1 C1

Half adder Half subtractor

A0
SD0
B0
E = 0: Half adder
E = 1: Half subtractor
E CB1
 Adder/Subtractor-1
Ci
Ai Di
Bi

Ci+1
E

E = 0: Full adder
E = 1: Full subtractor
 Reordered Full
Full Adder Full Adder Subtractor
Ci Ai Bi Si Ci+1 Ci Ai Bi Si Ci+1 Ci Ai Bi Di Ci+1
0 0 0 0 0 1 0 1 0 1 0 0 0 0 0
0 0 1 1 0 1 0 0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 1 1 1 0 1 0 1 0
0 1 1 0 1 1 1 0 0 1 0 1 1 0 0
1 0 0 1 0 0 0 1 1 0 1 0 0 1 1
1 0 1 0 1 0 0 0 0 0 1 0 1 0 1
1 1 0 0 1 0 1 1 0 1 1 1 0 0 0
1 1 1 1 1 0 1 0 1 0 1 1 1 1 1

NOT
Making a full subtractor
from a full adder
Ai Bi

C i+1 Full Adder Ci

Di
Four-Bit Parallel Adder
A B A B A B A B
3 3 2 2 1 1 0 0

C a rry
O ut
F .A 3
F .A 2 F .A 1 F .A 0
C 3
C 2 C 2 C 0

S 3
S 2
S 1 S 0
This circuit is sometimes referred to as a ripple-
through adder
C0 ripples through four two-level logic circuits
and hence the sum cannot be completed until
eight gate delays
For this kind of adder, the maximum delay is
directly proportional to the number of stages n.
 Adder/Subtractor-2
A3 B3 A2 B2 A1 B1 A0 B0

Full Adder Full Adder Full Adder Full Adder

C C2 C1
3

C4 SD 3 SD2 SD1 SD 0

E = 0: 4-bit adder
E = 1: 4-bit subtractor
Carry Look-Ahead Circuit
To improve the speed of addition
Consider the carry output equation for a full
Cout is
adder A BCin AB Cin ABC in ABCin

Cout can
Which ( A be in AB
B)Cexpressed as follows
Cout PCin G
or as P A B
where G AB
Carry Look-Ahead Circuit
Four a four-bit adder the generate and
propagate terms for eachG 0 stage
A0 B 0 are
P 0 A0 B 0
G1 A1 B1 P1 A1 B1
G 2 A2 B 2 P 2 A2 B 2
G 3 A3 B 3 P 3 A3 B 3
while the carries for the various stages are
C 0 P0 C 1 G0
C1 P1 C 0 G1
C 2 P 2 C1 G 2
C 3 P3 C 2 G 3
Carry Look-Ahead Circuit
Substituting for C0 in the C1 equation etc leads to
C1 P1P 0C 1 P1G 0 G1
the following equations:
C 2 P 2 ( P1P 0C 1 P1G 0 G1) G 2
C 3 P 3( P 2 ( P1P 0C 1 P1G 0 G1)) G 3
And the sum
S 0 A0 B 0 C 1 P 0 C 1
S 1 P1 C 0
S 2 P 2 C1
S 3 P3 C 2
Since the number of levels of logic required when a
large number of bits has to be added does not
increase then the Carry Look-Ahead adder will
provide a faster addition time
Binary Multiplication
A2 A1 A0
Paper and Pen method
B2 B1 B0
A2 B 0 A1B 0 A0 B 0
which is implemented using
A2 B1 A1B1 A0 B1
9 AND gates, 3 FA and
A2 B 2 A1B 2 A0 B 2
3 HA
C 3 C 2
C 4 C 3 C 2 C1
P5 P4 P3 P2 P1 P0