PLD Architectures and Testing

Contents :
Xillnx 9500 series CPLD (XC 9572).
Spartan III EFPGA (XC3S500E).
Testing: Fault models.
Path sensitizing random test design for testability.
Built-in self test, Boundary scans.
 THE EVOLUTION OF PLDs
PROMs, are memories that can be inexpensively programmed by the user to contain
a specific pattern.
This pattern can be used to represent a microprocessor program, a simple algorithm,
or a state machine.
Some PROMs can be programmed once only.
Other PROMs, such as EPROMs or EEPROMs can be erased and programmed
multiple times.
PROMs are excellent for implementing any kind of combinatorial logic with a
limited number of inputs and outputs.
For sequential logic, external clocked devices such as flip-flops or microprocessors
must be added.
Also, PROMs tend to be extremely slow, so they are not useful for applications
where speed is an issue.
 Programmable Logic Arrays (PLAs)
Programmable Logic Arrays (PLAs) were a solution to the speed and input
limitations of PROMs.
PLAs consist of a large number of inputs connected to an AND plane, where
different combinations of signals can be logically ANDed together according to how
the part is programmed.
The outputs of the AND plane go into an OR plane, where the terms are Ored
together in different combinations and finally outputs are produced.
At the inputs and outputs there are typically inverters so that logical NOTs can be
obtained.
These devices can implement a large number of combinatorial functions.
Generally PLAs have many more inputs and are much faster than PROM.
Programmable Logic Arrays (PLAs)

PLA Architecture
 Programmable Array Logic (PALs)
The Programmable Array Logic (PAL) is a variation of the PLA.
It has a wide, programmable AND plane for ANDing inputs together.
However, the OR plane is fixed, limiting the number of terms that can be ORed
together.
Other basic logic devices, such as multiplexers, Ex-Ors, and latches are added to the
inputs and outputs. Most importantly, clocked elements, typically flip-flops, are
included.
These devices are now able to implement a large number of logic functions including
clocked sequential logic need for state machines.
This was an important development that allowed PALs to replace much of the
standard logic in many designs.
PALs are also extremely fast.
Programmable Array Logic (PALs)

PAL Architecture
 CPLDs and FPGAs
Complex Programmable Logic Devices (CPLDs)

CPLDs are just like a large number of PALs in a single chip, connected to each other
through a cross point switch.
They use the same development tools and programmers.
They are based on the same technologies, but they can handle much more complex
logic and more of it.
macrocell is basic building block of CPLD.
Macrocell array is a prefabricated array of higher-level logic functions such as flip-
flops, .ALU functions, registers etc.
Complex Programmable Logic Devices (CPLDs)

CPLD Architecture
 Complex Programmable Logic Devices (CPLDs)
Function Blocks:
function blocks are designed to be similar to existing PAL architectures.
I/O Blocks:
The I/O block is used to drive signals to the pins of the CPLD device at the
appropriate voltage levels with the appropriate current.
Interconnect:
The CPLD interconnect is a very large programmable switch matrix that allows
signals from all parts of the device go to all other parts of the device.
Programmable Elements:
Different manufacturers use different technologies to implement the programmable
elements of a CPLD.
The common technologies are Electrically Programmable Read Only Memory
(EPROM), Electrically Erasable PROM (EEPROM) and Flash EPROM.
 Example CPLD Families
Some CPLD families from different vendors are listed below:
Altera MAX 7000 and MAX 9000 families
Atmel ATF and ATV families
Lattice ispLSI family
Lattice (Vantis) MACH family
Xilinx XC9500 family.
 Xilinx XC9500 family CPLD (XC9572).
The outline specification of the part of the XC9500 series of Xilinx Inc.
is shown below.
Xilinx XC9500 family CPLD (XC9572).
 Xilinx XC9500 family CPLD (XC9572).
An I/O block is composed of input buffer, output buffer, multiplexer
for the output control and grounding control and so on.
Multiplexer for the output control(OE MUX) controls an output
enable or stop.
It is controlled by the signal from the macrocell or the signal of the
GTS(Global Three-State control) pin.
There are two or four GTS pins.
A slew rate control is the one to make the rising and the falling of the
output pulse smooth.
It is used when suppressing the occurrence of the noise.
A grounding control is used when making input/output pin (I/O) an
earth terminal. (In case of the circuit where much noise occurs).
I/O Blocks
FastCONNECT Switch Matrix
 FastCONNECT Switch Matrix
FastCONNECT Switch Matrix controls the input signals to the
Function Block.

All the signals from the input-output port and the signals of the
Function Block are connected with FastCONNECT Switch Matrix.

The signals which are specified by the program are applied to the
Function Block.

The output signals from the Function Block are applied to the
Function Block through the wired AND buffer.

This provides additional logic capability and increases the effective

logic fan-in of the destination Function Block without any additional
timing delay.
Function Block
 Function Block

Function block is composed of the programmable AND array, product

term allocator and macrocell.

36 pieces of input signals are divided into the true and complement
signals by the programmable AND array and become 72 kinds of signals.

In Product Term Allocator, it applys the signal with combination of

them to the macrocell.

A macrocell is composed of one D/T type flip-flop. The signals of

set/reset/clock to this flip-flop are supplied by the Product Term
Allocator.
 Function Block
There are 18 independent macrocells in one Function Block .

18 pieces of output in the Function Block and they are connected with
FastCONNECT Switch Matrix and I/O blocks.

The set/reset signal(GSR : Global Set/Reset) and the clock

signal(GCK : Global Clocks) are used for the condition of the operation
of the flip-flop according to need.

PTOE(Product Term Output Enable) signal is output to I/O block

from Product Term Allocator.

The number of the Function Blocks depends on the device.

As for XC9536, 2 blocks are mounted, as for XC9572, 4 blocks are

mounted and as for XC95108, 6 blocks are mounted.
In-System Programming
 In-System Programming
XC9500 devices are programmed in-system via a standard 4-pin
JTAG(Joint Test Action Group) protocol.
The devices fully support IEEE 1149.1 boundary-scan(JTAG).
While programming, all input ports in the I/O block are set to the 'H
level.
The wires to use in JTAG are the following four. Each use is shown
below.
TMS(Test Mode Select):
This signal is decoded by the TAP controller to control test operations.
TCK(Test Clock):
This clock drives the test logic for all devices on boundary-scan chain.
TDI(Test Data In):
This signal is used to transmit serial test instructions and data.
Pin diagrams ( XC9536-PC44/XC9572-PC44 )

In case of XC9572-PC44,
they are 34 macrocells in the 72
macrocells.
The macrocells which don't
correspond to the input/output
pins can be used only in the
logic circuits inside.
Device Part Marking and Ordering Combination Information

* For More Details Refer Data sheet

Field Programmable Gate Arrays (FPGAs)
 Field Programmable Gate Arrays (FPGAs)

Logic blocks
to implement combinational
and sequential logic
Interconnect
wires to connect inputs and
outputs to logic blocks
I/O blocks
special logic blocks at periphery
of device for external connections
Key questions:
how to make logic blocks programmable? FPGA Architecture
how to connect the wires?
after the chip has been fabbed
 Field Programmable Gate Arrays (FPGAs)
The architecture consists of configurable logic blocks, configurable
I/O blocks, and programmable interconnect.
There is clock cktry for driving the clock signals to each logic block.
There will be additional logic resources such as ALUs, memory, and
decoders may be available.
The two basic types of programmable elements for an FPGA are Static
RAM and anti-fuses.
RAM-based:
memory bit controls a switch that connects/disconnects two wires.
typical connections are .5K-1K ohm.
can be programmed and re-programmed easily (tested at factory)
Fuse and anti-fuse:
fuse makes or breaks link between two wires.
typical connections are 50-300 ohm.
one-time programmable.
 (FPGA: CLB)
Configurable Logic Blocks:
It consists of a combinational logic array, program controlled data
multiplexers, and flip-flops.
The CLB contains RAM memory cells and can be programmed to
realize function of different variables.
5-input, 1 output function or two 4-input, 1 output functions.
optional register on outputs.
Built-in fast carry logic.
Can be used as memory.
Three types of routing
direct.
general-purpose.
long lines of various lengths.
RAM-programmable( can be reconfigured).
FPGA: Configurable Logic Blocks:

IOB IOB IOB IOB

IOB
CLB CLB

IOB
Wiring Channels

IOB
CLB CLB

IOB
 Configurable I/O Blocks
Configurable I/O Blocks:
Is used to bring signals onto the chip and send them back off again.

It consists of an input buffer and an output buffer with three state and
open collector output controls.

Typically there are pull up resistors on the outputs and sometimes pull
down resistors.

The polarity of the output can usually be programmed for active high
or active low output.

And often the slew rate of the output can be programmed for fast or
slow rise and fall times.

There is often a flip-flop on outputs so that clocked signals can be

output directly to the pins without encountering significant delay.
Configurable I/O Blocks
 FPGA: Programmable Interconnect:

long lines are used to connect critical CLBs that are physically far
from each other on the chip without inducing much delay.

short lines which are used to connect individual CLBs which are
located physically close to each other.

There is often one or several switch matrices, like that in a CPLD, to

connect these long and short lines together in specific ways.
 FPGA: Programmable Interconnect

Programmable switches allow the connection of CLBs to interconnect

lines and interconnect lines to each other and to the switch matrix.

Three-state buffers are used to connect many CLBs to a long line,

creating a bus.

Special long lines, called global clock lines, are specially designed for
low impedance and thus fast propagation times.

Global clock lines connected to the clock buffers and to each clocked
element in each CLB. This is how the clocks are distributed throughout
the FPGA.
 FPGA: Clock Circuitry

Special I/O blocks have clock drivers, which are distributed around
the chip which are connected to clock input pads and drive the clock
signals onto the global clock lines.

These clock lines are designed for low skew times and fast propagation
times.
 Spartan-3E FPGA Family((XC3S500E).)

The Spartan-3E family of Field-Programmable Gate Arrays (FPGAs)

is specifically designed to meet the needs of high volume, cost-sensitive
consumer electronic applications.

Architectural Overview:
The Spartan-3E family architecture consists of five fundamental
programmable functional elements:

Configurable Logic Blocks (CLBs) contain flexible

Look-Up Tables (LUTs) that implement logic plus storage elements
used as flip-flops or latches.
CLBs perform a wide variety of logical functions as well as store data.
 Spartan-3E FPGA Family((XC3S500E).)

Input/output Blocks (IOBs):

control the flow of data between the I/O pins and the internal logic of
the device.
Each IOB supports bidirectional data flow plus 3-state operation.
Supports a variety of signal standards, including four high-performance
differential standards.
Double Data-Rate (DDR) registers are included.

Block RAM :
Provides data storage in the form of 18-Kbit dual-port blocks.

Multiplier Blocks:
Accept two 18-bit binary numbers as inputs and calculate the product.
 Spartan-3E FPGA Family((XC3S500E).)

Digital Clock Manager (DCM) :

Blocks provide self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock signals.
Spartan-3E FPGA Family((XC3S500E).)