Delay-Fault Testing Tutorial

Acknowledgement: This presentation is adapted from

Professor Janak Patels tutorial on the same topic available
on the web at:
http://courses.ece.uiuc.edu/ece543/docs/DelayFault_6_per_page.pdf
 Outline
Common Fault Models (Review)
Defects and Delay Faults
Delay Fault Models
Transition Faults
Path Delay Faults
Robust Path Test
Non-robust Path Test

Delay Fault Testing Tu 2

 Common Fault Models
Fault Model Definition
Stuck-at Fault (SAF) Logic line stuck at 0 or 1
(can be single or multiple)
Bridging Signals x and y become
AND(x,y) or OR(x,y)
Stuck-open Signal x stuck in some
previous state
Delay An I/O path between clocked
elements has excessive delay
Coupling Signals x and y become F(x,y)
Pattern Interference Signals interact in space & time

Delay Fault Testing Tu 3

Delay Fault Testing Tu 4
Delay Fault Testing Tu 5
Delay Fault Testing Tu 6
Delay Fault Testing Tu 7
Delay Fault Testing Tu 8
Delay Fault Testing Tu 9
Delay Fault Testing Tu 10
Delay Fault Testing Tu 11
Delay Fault Testing Tu 12
Delay Fault Testing Tu 13
Delay Fault Testing Tu 14
Delay Fault Testing Tu 15
 Only if no other path delay is increased.

Delay Fault Testing Tu 16

Delay Fault Testing Tu 17
Delay Fault Testing Tu 18
Delay Fault Testing Tu 19
Delay Fault Testing Tu 20
Delay Fault Testing Tu 21
Delay Fault Testing Tu 22
 Exercise
Consider the 4-Nand implementation of the
XOR gate in the previous slide. There are
six I/O paths hence 12 path delay faults. For
each of these faults, determine if it is
robustly testable, only non-robustly testable
or not testable (functionally redundant).
Provide justification for your answers.

Delay Fault Testing Tu 23

Delay Fault Testing Tu 24
Delay Fault Testing Tu 25
Broadside is also called launch-off-capture test.
Skewed-Load is also called launch-off-shift test.

Delay Fault Testing Tu 26

Delay Fault Testing Tu 27
Delay Fault Testing Tu 28
 Timing for
launch-off-
capture
Transition-delay
fault testing

IC: Initialization Clock

LC: Launch Clock
CC: Capture Clock
SEN: Scan Enable

This figure is borrowed from the paper, Ahmed et al., ITC-2005, Paper 11.1
Delay Fault Testing Tu 29
Delay Fault Testing Tu 30
 Timing for
launch-off-shift
Transition-
delay fault
testing

IC: Initialization Clock

LC: Launch Clock
CC: Capture Clock
SEN: Scan Enable

Delay
This figure is borrowed from FaultAhmed
the paper, Testing TuITC-2005, Paper 11.131
et al.,
Delay Fault Testing Tu 32
Delay Fault Testing Tu 33
(See Prof. Patels website for details on Segment Test)
Delay Fault Testing Tu 34
Delay Fault Testing Tu 35
Delay Fault Testing Tu 36