DESIGN FOR

TESTABILITY

N.Pitcheswara Rao
Assistant Professor
ECE Department
Testing Philosophy
Example 1.1

Testing of students. In a course on xyzeeology, 70% of the students

deserve to pass. We will call them pass quality students.

Assuming that the number of students in the class is large, we will

study the test process using a statistical basis. For a randomly

selected student from the class, we define the following events:

PQ: student is pass quality P: student passes the test

FQ: student is fail quality F: student fails the test

 In our example, Prob(PQ)=0.7 Assuming that only
pass/fail grades are awarded,the remaining 30%
students are of fail quality, i.e., Prob(FQ)=0.3
As we know, it is impossible to design a perfect test.
However, our teacher does quite well and 95% of pass
quality students actually pass the test.
This is represented by conditional probabilities, Prob(P|
PQ)=0.95 and Prob(F|PQ)=0.05 Similarly, the test
correctly fails 95% of the fail quality students.
A pass/fail test.
The test separates them into two groups
shown on the right as passed and
failed. Sizes of the passed and failed
groups created by the test are given by
the total probabilities of passing and
failing, respectively. The total probability
of passing is,
Functional Versus Structural
Testing
Testing of a ten-input AND function
Suppose that we apply an input pattern 0101010101,
and observe a 0 output. This is a correct output, but
what can we conclude: the gate under test is (A) an
AND, (B) not a NAND, (C) not a NOR, or (D) not an OR
function?
Since the obtained output violates the truth tables of
NAND and OR gates, only (B) and (D) are correct
answers.
We could use another pattern, 1111111111, to make
sure that the gate is not a NOR. However, that does not
guarantee that the given circuit will function correctly as
an AND gate for all possible input patterns.
Conti..
Given ten inputs, it is possible to construct Boolean
functions, and in the present situation our functional test
must allow us to conclude that the function is AND and
not one of the others.
A complete functional test will check each entry of the
truth table. Though possible with ten inputs, such a test
will be too long and impossible to use with a real circuit
with several hundred input lines.
Difficult as it is, the use of functional tests is often found
necessary for verification of design.
Conti..
which focuses on hardware test.
The purpose of hardware test (also referred to as
manufacturing test) is to discover any faults caused due
to manufacturing defects or errors. A basic assumption
made is that the design being manufactured is correct.
Back in 1959, Eldred derived tests that would observe
the state of internal signals at primary outputs of a large
digital system [215]. Such tests are called structural
because they depend on the specific structure (gate
types, interconnects, netlist) of the circuit.
One of the greatest advantages of structural testing is
that it allows us to develop algorithms. Central to these
algorithms are fault models.
Levels of Fault Models
Modeling of faults is closely related to the modeling of
the circuit. In the design hierarchy, the level refers to
the degree of abstraction.
The register-transfer level (RTL) or logic level consists of
a netlist of gates and the stuck-at faults at this level are
the most popular fault models in digital testing.
Other fault models at this level are bridging faults and
delay faults. Bridging faults are discussed in various
places in this book and Chapter 12 focuses
A Glossary of Fault Models
Assertion Fault: An assertion expresses a property of a

high-level function in the form: antecedent

consequent, where antecedent and consequent can be

simple predicates like line L takes symbolic value v or

conjunctions of simple predicates. An assertion fault

means that the corresponding property is not true for

some input of the system. This fault model has been

used for generating tests for a microprocessor [713].

 Behavioral Faults: When the behavior of an electronic
system is described in computer-readable form, it is
generally written in a programming language (such as C)
or some other hardware description language that
resembles a programming language.

Behavioral faults refer to incorrect execution of the

language constructs used in the description.
Examples of behavioral faults are assertion faults,
branch faults, and instruction faults.
 Branch Fault: This fault is modeled at the behavioral
level where the circuit function is described in a
programming language. A branch fault affects a branch
statement and causes it to branch to an incorrect
destination.
 Bridging Fault: Usually modeled at the gate or
transistor level, a bridging fault represents a short
between a group of signals. The logic value of the
shorted net may be modeled as 1-dominant (OR bridge),
0-dominant (AND bridge), or indeterminate, depending
upon the technology in which the circuit is implemented.
Non-feedback bridging faults are combinational and their
coverage by stuck-at fault tests is normally very high.

Bridging faults are often used as examples of defect-

oriented faults
 Bus Fault: A bus fault specifies the status for each line
in a bus as stuck-at-0, stuck-at-1, or fault-free. Thus, for
an n-bit bus, there are 3 n-1 bus faults.
A total bus fault assumes all lines of the bus to be stuck
at the same 0 or 1 state
 Cross-point Fault: These faults are modeled in
programmable logic arrays (PLA.) In the layout of a PLA, input
and output variable lines are laid out perpendicular to the
product-lines.
Crossing signal lines either form specific types of connections
or remain unconnected at cross-points, depending on the
function implemented.
There are two types of cross-point faults. A missing cross-point
means
a missing connection at a crossing where a connection was
intended. An extra crosspoint means a faulty connection at a
crossing where no connection was intended.
Based on their influence on the logic function of the PLA, the
cross-point faults are further classified as shrinkage, growth,
appearance, and disappearance faults.
 Defect-Oriented Faults: Faults at the physical level
that usually occur during manufacture are called
defects. The electrical or logic-level faults that can be
produced by physical defects are classified as defect-
oriented faults.
Examples of physical defects are broken (open) wires,
bridges, improper semiconductor doping, and improperly
formed devices.
 Delay Fault: These faults cause the combinational
delay of a circuit to exceed the clock period. Specific
delay faults are transition faults, gate-delay faults, line-
delay faults, segment-delay faults, and path-delay faults.
 Gate-Delay Fault: The fault increases the input to
output delay of a single logic gate, while all other gates
retain some nominal values of delay. The increase in the
delay of the faulty gate is called the size of the gate-
delay fault.
 Hyperactive Fault: A hyperactive fault causes a large
number of signals in the circuit to differ from their
correct values.
The fault thus produces very high fault related activity in
the circuit. If not readily detected, fault simulators
usually remove hyperactive faults for later consideration
to save CPU time and memory
 Initialization Fault: Circuits with memory elements
(e.g., flip-flops) are designed so that they can be
initialized by applying suitable input signals.
Faults that interfere with such an initialization procedure
are called initialization faults.
A typical example of such a fault is the clock line of a
flip-flop being stuck in the inactive state.
 Initialization Fault. In the circuit of Figure 4.1, consider a
fault that permanently grounds the signal A. Such a fault
is called a stuck-at-0 fault and will be discussed in detail
in Section 4.5. In our notation, where the faulty value
differs from the correct value, the faulty value is shown
in parentheses. We assume that the initial state of the
circuit (i.e., output Q of the flip-flop FF) is unknown,
denoted as X. To set Q to 0, we apply . and . After the
application of the clock CK, the fault-free circuit output
is initialized to 0, but the faulty circuit remains in the
unknown state. Such a fault that prevents the circuit
from being initialized is called an initialization fault.
 Instruction Fault: Usually modeled in programmable
systems like microprocessors or digital signal processors,
an instruction fault causes an intended instruction to be
incorrectly executed.
 Intermittent Fault: A fault that appears and
disappears as a function of time is called an intermittent
fault. A fracture in an interconnect may produce an
intermittent open for some time before it becomes a
permanent fault. Intermittent faults can be of any type,
e.g., stuck-at fault or a bridging fault, with its presence
in time described probabilistically
 Line-Delay Fault: This fault models rising and falling
delays of a given signal line. In contrast with the
transition fault where the transition can be propagated
through any path, a test for a line-delay fault must
propagate the transition through the longest sensitizable
path.
 Logical Faults: These faults affect the state of logic
signals. Normally, the state may be modeled as {0, 1, X
(unknown), Z (high impedance)}, and a fault can
transform the correct value to any other value. Several
types of faults can be modeled at the logic level.
However, the term logical faults often implies stuck-at
faults.
 Memory Faults: Faults modeled in memory blocks are
single cell stuck-at-[0,l] faults, pattern sensitive faults,
cell coupling faults, and single stuck-at faults in the
address decoder logic
 Multiple Fault: A multiple fault represents a condition
caused by the simultaneous presence of a group of
single faults. Frequently considered multiple faults
consist of the same type of single faults
Multiple stuck-at faults are usually not considered in
practice because of two reasons:
1. The number of multiple stuck-at faults in a circuit with
n single fault sites is 3n-1 which is too large a number
even for circuits of moderate size.
2. Tests for single stuck-at faults are known to cover a
very high percentage (greater than 99.6%) of multiple
stuck-at faults when the circuit is large and has several
outputs.
 Example 4.3 Multiple stuck-at faults. The circuit of Figure 4.2 has
three redundant stuck-at faults: shown as F1, F2, and F3. A set of
three vectors, 00, 01, and 10, detects all other single stuck-at faults.
A set of multiple faults contains all possible combinations of single
faults. If any one of the single fault components of a multiple fault is
detectable then there is a good chance that the multiple fault will be
detected.
Following Gharaybeh et al. [245], we will define a multiply-testable
stuck-at fault as one where all single fault components are
redundant. This circuit has four such faults that are shown in the
table in Figure 4.2. Two of these, (F1,F2) and (F1,F3), produce the
same output functions as the original circuit and are redundant. The
other two faults, (F2,F3) and (F1,F2,F3), change the output function
and are detectable by a vector, 11. However, this vector was not in
the original single fault test set. So, the circuit, though faulty, will
pass the tests.
 Non-classical Fault: Although a non-classical fault, in
general, refers to a fault other than a stuck-at fault, the
term has been used for the stuck-open and stuck-short
faults of MOS technologies
 Oscillation Fault: These faults cause oscillating signals
in the faulty circuit when the fault-free circuit remains
stable. Such a condition can occur due to certain single
stuck-at faults in sequential circuits that contain
combinational feedback.
Oscillations can also occur in a purely combinational
circuit if a bridging fault produces feedback.
Oscillation faults are also referred to as star-faults
 Parametric Fault: Such a fault changes the values of
electrical parameters of active or passive devices from
their nominal or expected values.
Examples are the threshold voltage of a transistor
(active device) and values of resistors and capacitors
(passive devices.)
 Path-Delay Fault: This fault causes the cumulative
propagation delay of a combinational path to increase
beyond some specified time duration. The combinational
path begins at a primary input or a clocked flip-flop,
contains a connected chain of logic gates, and ends at a
primary output or a clocked flip-flop. The specified time
duration can be the duration of the clock period (or
phase), or the vector period.
Propagation delay is defined for the propagation of a
signal transition through the path. Thus, for each
combinational path there are two path-delay faults,
which correspond to the rising and falling transitions,
respectively.
 Pattern Sensitive Fault: This fault causes an incorrect
behavior in a certain part of the circuit only when a
specific state occurs in some other part.
Usually modeled in memories, a typical example is a
fault condition that prevents writing a 1 in a memory cell
when its physical neighbors have 0s stored in them.
 Permanent Fault: Any faulty behavior that does not
change with time is called a permanent fault. Faults that
are not permanent and affect the circuit only at certain
times (often at random instants) are called intermittent
faults.
 Physical Faults: These faults cause physical changes in
the circuit. Examples of physical faults are broken wires,
bridges (shorts) between conductors carrying
unconnected signals, shorted or open transistors, etc.
These faults also sometimes referred to as defect-
oriented faults.
 Pin Fault: When a circuit is modeled as an interconnect
of modules, the terminals of those modules are referred
to as pins. This term is adopted from the technology of
printed circuit boards (PCBs), which contain
interconnecting wiring between the pins of the mounted
chips.
Pin faults are the stuck-at faults on the signal pins (not
power and ground pins) of all modules in the circuit.
Pin faults are commonly modeled in high-level designs
where the internal gate-level structure of modules may
not be known.
 PLA Faults: A programmable logic array (PLA) is a
physical implementation of two-level AND-OR
combinational logic. The design consists of three sets of
parallel wires: inputs, product-terms, and outputs.
1. Stuck-at faults on inputs and outputs.
2. Cross-point faults
3. Bridging faults
 Potentially Detectable Fault: When a test is applied
to a sequential circuit, certain faults produce an
unknown state at the output when a deterministic output
is expected in the fault-free circuit.
This condition is known as potential (or probabilistic)
detection.
 Quiescent Current Fault: (I DDQ) These faults are
relevant to the CMOS (complementary metal oxide
semiconductor) technology. In the steady state (i.e.,
when the gate is not switching) the CMOS logic gate
provides no conducting path between the power supply
and ground.
Thus, the steady state current, also known as the
leakage or quiescent current (IDDQ), of a CMOS gate is on
the order of only a few microamperes.
 Race Fault: Stuck-at faults that cause a race condition
in the circuit are called race faults. For a certain initial
state and input, the final state of an asynchronous
sequential circuit can vary depending on specific delays
of its logic gates. Such a condition is known as a race.
 Redundant Fault: Consider a combinational circuit. Any
fault that does not modify the input-output function of
the circuit is called a redundant fault.
A redundant fault cannot be detected by any test. Such
faults can be removed from the circuit without changing
its output function.
 Example 4.4 Redundant stuck-at fault. Consider the
circuit shown in Figure 4.3(a). Its output function B is
Now suppose that the B input of the NAND gate has a s-
a-1 fault. Then the output of the NAND gate will be This
will produce a function at the output of the circuit, which
is the same as the fault-free function. This fault is,
therefore, redundant.
The reader can verify that no values of A and B will
produce different outputs from the faulty and fault-free
circuits.
 Since the circuit is combinational, this fault can be
removed by a simple procedure: The fanout of B on
which the fault lies is deleted and the corresponding
input of the NAND gate is set to 1. The output of the
NAND gate is now and it can be replaced by a NOT gate.
 Segment-Delay Fault: A segment of length L is a chain
of L combinational gates. Such a segment can be
contained in one or more input to output paths.
A segment-delay fault increases the delay of a segment
such that all paths containing the segment will have a
path-delay fault.
 Structural Faults: The structure of a circuit may refer
to its topology or to physical geometry. However, the
term structural faults is commonly used not for faults
modeled in the layout, but rather in gate-level
interconnects.
Examples of structural faults are single stuck-at faults
and bridging faults.
 Stuck-at Fault: This fault is modeled by assigning a
fixed (0 or 1) value to a signal line in the circuit. A signal
line is an input or an output of a logic gate or a flip-flop.
The most popular forms are the single stuck-at faults,
i.e., two faults per line, stuck-at-1 (s-a-1 or sal) and
stuck-at-0 (s-a-0 or sa0.)