Digital IC Design: Faculty-In-Charge: Dr. Sitangshu Bhattacharya

Digital IC Design
Faculty-in-charge: Dr. Sitangshu Bhattacharya

Department of ECE
Indian Institute of Information Technology-Allahabad
Room No. 2221, CC-I
Telephone: 2131
Email: sitangshu@iiita.ac.in
Digital IC Design
Contents:
o MOS Transistor: Structure, External Bias, o Dynamic Logic Circuits Pass transistors, Voltage
Operation, Current-Voltage Characteristics, Bootstrapping, Synchronous Dynamic Circuit
Capacitances, Small Geometry Scaling Testing, Dynamic CMOS Circuit Techniques, High
performance Dynamic CMOS circuits
o MOS Inverters: Resistive Load Inverter, n-type
MOSFET load inverter, CMOS inverter o Semiconductor Memories DRAM, SRAM, Non-
volatile, Flash Memory, FRAM
o Switching Characteristics and Interconnect
Effects: Delay Time and constraints, Interconnect o Low Power CMOS Logic Circuits Low Power
parasitics, Interconnect delay calculation, Switching Design Switching Activity, Switched Capacitance,
power dissipation of CMOS inverters Adiabatic Logic Circuits
o Combinational MOS Logic Depletion Logic o BiCMOS Logic Circuits BJT, Dynamic behavior,
Circuits with nMOS loads, CMOS logic circuits, BiCMOS static behavior Switching Delay
CMOS transmission gates
o Chip I/O Circuits ESD protection, Output Circuit
o Sequential MOS Logic Bistable elements, SR Noise, On Chip Clock Generation and Distribution,
Latch, Clocked Latch with FF circuits, CMOS D- Latchup and its prevention
latch and Edge Triggered FFs
Reading Materials:
1. CMOS Digital Integrated Circuits Analysis and Design By S-Mo Kang and Y Leblebici
2. Digital Integrated Circuits: Analysis and Design By John E. Ayers
3. Digital Integrated Circuits: A Design Perspective By Anantha P. Chandrakasan,
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017 Borivoje Nikolic, and Jan M. Rabaey
Digital IC Design
Combinational MOS Logic

See Kang and Leblebici Book
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design
Complex Designs: Stick Diagram: Eulers Rule

Provides Optimization in Stick/Layout Diagrams
Do the CMOS XOR stick diagram

Digital IC Design
AOI and OAI Gates
OAI: OR-AND-Inverter Gate
AOI: AND-OR-Inverter Gate

Digital IC Design
AOI and OAI Gates
OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)
AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Digital IC Design
AOI and OAI Gates

Digital IC Design
AOI and OAI Gates

Digital IC Design
AOI and OAI Gates

Digital IC Design
AOI and OAI Gates

Digital IC Design
Pseudo nMOS Gates

Digital IC Design
Pseudo nMOS Gates

Digital IC Design
Pseudo nMOS Gates

Digital IC Design
Pseudo nMOS Gates

Digital IC Design
Pseudo nMOS Gates

Digital IC Design
Pseudo nMOS Gates

Digital IC Design
Pseudo nMOS Gates
PUN: Pull Up Network

PDN: Pull Down Network

Digital IC Design
Pseudo nMOS Gates

Digital IC Design
Pseudo nMOS Gates: Power and size issues

Digital IC Design
Pseudo nMOS Gates: Ratioed Logic

Digital IC Design
Pseudo nMOS Gates-Example

Digital IC Design

Digital IC Design

Digital IC Design

Digital IC Design

Digital IC Design

Digital IC Design
CMOS One Bit Full-Adder
Homework: Dram the CMOS gate level diagram and stick diagram

Digital IC Design
Pass transistors/gates or transmission gates
A and B are controlled by signal

Digital IC Design
TG acts as a bi-directional switch between A and B are controlled by signal C

Digital IC Design
When C is high (VDD) both MOSFETs are ON: current can pass from A to B
(low resistance)

Digital IC Design
When C is low (0) both MOSFETs are OFF: current cant pass from A to B
(high impedance)

Digital IC Design
Substrate terminals of NMOS is grounded and PMOS is at V DD. Careful! with .

Digital IC Design
Operation of pass transistors/gates or transmission gates
Let input A is at constant high voltage VDD.

Digital IC Design
Let input A is at constant high voltage VDD.
Control signal is also high (both TGs are ON).
Vout is connected to a cap, C.

Digital IC Design
For nMOS:

Digital IC Design
For nMOS:
Will turn off for VDD- VT,n <Vout

Digital IC Design
For nMOS:
Will turn off for VDD- VT,n <Vout
Will go to saturation when VDD- VT,n >Vout

Digital IC Design
For pMOS:
Will be in the linear region for |VT,p| < Vout
Will go to saturation when |VT,p| > Vout

Digital IC Design
Total current:
Equivalent resistance :
(for total: do parallel )

Digital IC Design
Resistance in Region 1:

Digital IC Design

Digital IC Design

Digital IC Design

Digital IC Design
Representation of TGs

Digital IC Design
2 Input Multiplexor using TGs
If S = 0, B passes, A fails
If S = 1, B fails, A passes

Digital IC Design
8 Transistors-XOR CMOS
2CMOS TGs
2 CMOS inverters

Digital IC Design
6 Transistors-XOR CMOS

Digital IC Design
3 Variable Boolean Function CMOS TG

Digital IC Design: Faculty-In-Charge: Dr. Sitangshu Bhattacharya

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Digital IC Design

Faculty-in-charge: Dr. Sitangshu Bhattacharya

Combinational MOS Logic

Combinational MOS Logic

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Complex Designs: Stick Diagram: Eulers Rule

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate

AOI: AND-OR-Inverter Gate

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)

AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)

AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)

AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)

AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)

AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Pseudo nMOS Gates

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Pseudo nMOS Gates

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Pseudo nMOS Gates

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Pseudo nMOS Gates

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Pseudo nMOS Gates

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Pseudo nMOS Gates

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Pseudo nMOS Gates

PUN: Pull Up Network

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Pseudo nMOS Gates

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017