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MICROPROCESSOR

UNIT I
SYLLABUS
UNIT I INTRODUCTION
Evolution of Microprocessors, Microcontrollers and
Computers, Microprocessor based system design
need-steps, Advantages and limitations
organization of a microcomputer, Bus system
Decoders Tri state logic Interrupts Memory
devices: classifications and its interfacing Data
Transfer Concepts, Methods Parallel I/O
interfacing Serial I/O interfacing concepts Use of
SID and SOD lines DMA method of transfer.
Microprocessor and Microcontroller
Microprosessor
Microprocessor is an IC which has only the CPU inside
them.
These microprocessors dont have RAM, ROM, and
other peripheral on the chip.
A system designer has to add them externally to make
them functional. Application of microprocessor
includes Desktop PCs, Laptops, notepads etc.
Microcontroller
Microcontrollers are designed to perform specific
tasks. Specific means applications where the
relationship of input and output is defined.
Depending on the input, some processing needs to be
done and output is delivered.
EVOLUTION OF MICROPROCESSORS

Microprocessors were categorized into five generations:


First
Second
Third
Fourth
Fifth
Their characteristics are described below:
First-generation

The microprocessors that were introduced in 1971


to 1972 were referred to as the first generation
systems.
First-generation microprocessors processed their
instructions seriallythey fetched the instruction,
decoded it, then executed it.
When an instruction was completed, the
microprocessor updated the instruction pointer
and fetched the next instruction, performing this
sequential drill for each instruction in turn.
Second generation

By the late 1970s, enough transistors were available on the IC to


usher in the second generation of microprocessor sophistication:
16-bit arithmetic and pipelined instruction processing.
Motorolas MC68000 microprocessor, introduced in 1979, is an
example. Another example is Intels 8080.
This generation is defined by overlapped fetch, decode, and
execute steps (Computer 1996). As the first instruction is
processed in the execution unit, the second instruction is decoded
and the third instruction is fetched.
The distinction between the first and second generation devices
was primarily the use of newer semiconductor technology to
fabricate the chips.
This new technology resulted in a five-fold increase in instruction,
execution, speed, and higher chip densities.
Third generation

The third generation, introduced in 1978, was


represented by Intels 8086 and the Zilog Z8000, which
were 16-bit processors with minicomputer-like
performance.
The third generation came about as IC transistor counts
approached 250,000.
Motorolas MC68020, for example, incorporated an on-
chip cache for the first time and the depth of the
pipeline increased to five or more stages.
This generation of microprocessors was different from
the previous ones in that all major workstation
manufacturers began developing their own RISC-based
microprocessor architectures (Computer, 1996).
Fourth generation
As the workstation companies converted from
commercial microprocessors to in-house designs,
microprocessors entered their fourth generation with
designs surpassing a million transistors.
Leading-edge microprocessors such as Intels
80960CA and Motorolas 88100 could issue and retire
more than one instruction per clock cycle.
Fifth generation

Microprocessors in their fifth generation, employed


decoupled super scalar processing, and their design
soon surpassed 10 million transistors.
In this generation, PCs are a low-margin, high-volume-
business dominated by a single microprocessor.
Microprocessor based system design
Feasibility Study
Provides background for actual system
development.
Helps in the selection of particular level of
technology depending on the availability of
expertise to operate and maintain the product.
Analyses various approaches like purchasing a
system and modifying or designing the
system.
System Specification
System development is done.
A system is defined in terms of set of entities
and the relation between entities.
The inputs and outputs are called the
environment of the system.
Initial Design
It defines the functions that will be carried
out by both hardware and software.
Analysis of the problem should be done to
define performance requirements,
hardware and software routines.
Hardware Design
The matching of electrical characteristics
and timing of ICs is done using a complete
microprocessor and peripheral chips.
Software Design
This involves the following steps
Environment and problem specification( data
format, data transfer)
State transition diagram
Flowchart
Memory I/O and register organization
Editing and assembling

Test and debug


Testing should be done by simulating the
environment in which the module is to work.
Once the tests are successfully completed, actual
software is tested block by block.
Integration
Integration of hardware and software is
carried out and the system is simulated
under real/simulated conditions.
Documentation
It helps in the coordinated approach to
system development.
The system specifications, environment,
hierarchical chart, flowchart, state
transition diagrams, test procedures etc.
should be included in the documentation.
Organization of
Microcomputer
The basic components
of a microcomputer are:
1) CPU
ALU
Control
Register
2) Program memory
3) Data memory
4) Output ports
5) Input ports
6) Clock generator.
Central Processing Unit:
The CPU consists of ALU (Arithmetic and Logic Unit),
Register unit and control unit.
The CPU retrieves stored instructions and data word
from memory; it also deposits processed data in
memory.
ALU (Arithmetic and Logic Unit)
This section performs computing functions on data.
These functions are arithmetic operations such as
additions subtraction and logical operation such as
AND, OR rotate etc.
Result are stored either in registers or in memory or
sent to output devices.
Register Unit:
It contains various register. The registers are used
primarily to store data temporarily during the
execution of a program.
Some of the registers are accessible to the users
through instructions.
Control Unit:
It provides necessary timing & control signals
necessary to all the operations in the microcomputer.
It controls the flow of data between the processor and
peripherals (input, output & memory).
The control unit gets a clock which determines the
speed of the microprocessor.
Program Memory:
The basic task of a microcomputer system is to ensure that
its CPU executes the desired instruction sequence in the
program properly.
The instruction sequence is started in the program memory
on initialization- usually a power up and manual reset, the
processor starts by executing the instruction in a
predetermined location in program memory.
Data Memory:
A microcomputer manipulates data according to the
algorithm given by the instruction in the program in the
program memory.
These instruction may require intermediate results to be
stored, the functional block in c have same internal
registers which can also be used if available for such
storage. External data memory is needed if the storage
requirements is more.
Input / Output Ports:
The input & output ports provide the microcomputer
the
capability to communicate with the outside world.
The input ports allow data to pass from the outside
world to the c data which will be used in the data
manipulation being done by the microcomputer to
send data to output devices
Clock Generator:
Operations inside the microprocessor, are usually
synchronous by nature.
The clock generator generates the appropriate clock
periods during which instruction executions are
carried out by the microprocessor
Bus system of
Microcomputer
Address Bus:
The address bus consists of 16, 20, 24, or more
parallel signal lines, through which the CPU sends out
the address of the memory location.
This memory location is used to write to or read from.
The number of memory location is 2 to the power N
address lines.
Data Bus:
The data bus consists of 8, 16, 32 or more parallel
signal lines.
The data bus lines are bidirectional.
This means that the CPU can read data from memory
or from a I/O port as well as send data to a memory
location or to a I/O port.
Control Bus:
The control bus consists of 4-10 parallel signal lines.
The CPU sends out signals on the control bus to
enable the outputs of addressed memory devices or
port devices.
Typically control bus signals are memory read,
memory write, I/O read and I/O write.
To read a data from a memory location, the CPU
sends out the address of the desired data on the
address bus and then sends out a memory read signal
on the control bus.
Address Decoder
Logical circuit that identifies each combination of
signals present at input
An address decoder is a binary decoder circuit that
has two or more bits of an address bus as inputs and
that has one or more device selection lines (I/O
peripherals or memory) as outputs.
When the address for a particular device appears on
the address bus, the address decoder asserts the
selection line for that device.
Tri-state Logic
Has three logic states: logic 0, logic1 and high impedance
Has three lines: input, output and enable line
When enable is activated, tri-state device acts as a
normal device
When enable is deactivated, the logic device goes to high
impedance state ( i.e, disconnected from the system)
Hence the peripherals do not load the bus system
Used when Microprocessor allow multiple logic devices to
be connected to the same wire or bus without damage or
loss of data
Logically Truth Table
A A enable A Output
0 0 (Z)
enable 0 1 (Z)
1 0 1
1 1 0
26
Interrupts
Interrupt is a mechanism by which an I/O or an
instruction can suspend the normal execution of
processor and get itself serviced.
Generally, a particular task is assigned to that
interrupt signal.
In the microprocessor based system the
interrupts are used for data transfer between the
peripheral devices and the microprocessor.
The processor will check the interrupts always at
the 2nd T-state of last machine cycle.
Interrupt Service Routine(ISR):
A small program or a routine that when executed
services the corresponding interrupting source is
called as an ISR.

Classification of interrupts:
Maskable/Non-Maskable Interrupt
An interrupt that can be disabled by writing some
instruction is known as Maskable Interrupt
otherwise it is called Non-Maskable Interrupt.
Hardware / Software Interrupts
Vectored/ Non vectored Interrupts
Hardware interrupts:
An external device initiates the hardware interrupts and
placing an appropriate signal at the interrupt pin of the
processor.
If the interrupt is accepted then the processor executes
an interrupt service routine.
The 8085 has five hardware interrupts
(1) TRAP (2) RST 7.5 (3) RST 6.5
(4) RST 5.5 (5) INTR
Software Interrupts:
A software interrupts is a particular instructions that can
be inserted into the desired location in the program.
There are eight Software interrupts in 8085
Microprocessor.
From RST0 to RST7
Vectored and non vectored interrupts

INTR non vectored interrupt


8085 Interrupts and Vector Locations
TRAP:
This interrupt is a non-maskable interrupt. It is
unaffected by any mask or interrupt enable.
TRAP bas the highest priority and vectored
interrupt.
TRAP interrupt is edge and level triggered. This
means that the TRAP must go high and remain
high until it is acknowledged.
In sudden power failure, it executes a ISR and
send the data from main memory to backup
memory.
The signal, which overrides the TRAP, is HOLD
signal. (i.e., If the processor receives HOLD and
TRAP at the same time then HOLD is recognized
first and then TRAP is recognized).

There are two ways to clear TRAP interrupt.


RST 7.5:
The RST 7.5 interrupt is a maskable interrupt.
It has the second highest priority.
It is edge sensitive. ie. Input goes to high and no
need to maintain high state until it recognized.
Maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.
Enabled by EI instruction.
RST 6.5 and 5.5:

The RST 6.5 and RST 5.5 both are level


triggered. . ie. Input goes to high and stay high
until it recognized.
Maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.
Enabled by EI instruction.
The RST 6.5 has the third priority whereas RST
5.5 has the fourth priority.
INTR:
INTR is a maskable interrupt. It is disabled by,
1.DI instruction
2.System or processor reset.
3.After reorganization of interrupt.
Enabled by EI instruction.
Non- vectored interrupt. After receiving INTA
(active low) signal, it has to supply the address of
ISR.
It has lowest priority.
It is a level sensitive interrupts. ie. Input goes to
high and it is necessary to maintain high state
until it recognized.
The following sequence of events occurs when INTR
signal goes high.
1. The 8085 checks the status of INTR signal during
execution of each instruction.
2. If INTR signal is high, then 8085 complete its current
instruction and sends active low interrupt
acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic
places an instruction OPCODE on the data bus. In the
case of multibyte instruction, additional interrupt
acknowledge machine cycles are generated by the
8085 to transfer the additional bytes into the
microprocessor.
4. On receiving the instruction, the 8085 save the
address of next instruction on stack and execute the
received instruction
SIM
RIM
Memory Devices
Classification of RAM
Memory Interfacing
Consider a system in which the full memory space 64kb
is utilized for EPROM memory. Interface the EPROM with
8085 processor.
The memory capacity is 64 Kbytes. i.e
2^n = 64 x 1000 bytes where n = address lines.
So, n = 16.
In this system the entire 16 address lines of the
processor are connected to address input pins of memory
IC in order to address the internal locations of memory.
The chip select (CS) pin of EPROM is permanently tied to
logic low (i.e., tied to ground).
Since the processor is connected to EPROM, the active
low RD pin is connected to active low output enable pin
of EPROM.
The range of address for EPROM is 0000H to FFFFH.
Consider a system in which the available 64kb
memory space is equally divided between EPROM and
RAM. Interface the EPROM and RAM with 8085
processor.
Implement 32kb memory capacity of EPROM using
single IC 27256.
32kb RAM capacity is implemented using single IC
62256.
The 32kb memory requires 15 address lines and so the
address lines A0 - A14 of the processor are connected
to 15 address pins of both EPROM and RAM.
The unused address line A15 is used as to chip select.
If A15 is 1, it select RAM and If A15 is 0, it select
EPROM.
Inverter is used for selecting the memory.
The memory used is both Ram and EPROM, so the low
RD and WR pins of processor are connected to low WE
and OE pins of memory respectively.
Data Transfer
Data transfer schemes are dependent on on-
line or off-line processing,type of I/O
device(capable of parallel or serial data
transfer,synchronous or asynchronous) and the
particular application.
Data transfer schemes may be categorized into
parallel data transfer and serial data transfer.
Parallel data transfer can be further
categorized into programmed I/O, interrupt I/O
and direct memory access.
Parallel data transfer-
In parallel data transfer,a group of bits(for example 8-
bits) are transmitted from one device to another at any
time.
To achieve parallel data transfer,a group of data lines
will be conducting the processor and peripheral devices.
Normally in microprocessor based system the parallel
data transfer schemes are adopted to transfer data
between various devices inside the system.
Programmed I/O
In programmed I/O,the data transfer is controlled by
the user program being executed.
Depending on the type of the device,data transfer may
be asynchronous or synchronous.
Synchronous data transfer is used when the I/O device
matches in speed with the speed of microprocessor else
Asynchronous data transfer.
Interrupt I/O
Interrupt driven data transfer scheme is the
best method of data transfer for efficient
utilization of the microprocessor time.
In this scheme, the processor initiates the I/O
device for data transfer.
After initiating the device, the microprocessor
will continue the execution of instruction in the
program.
Also at the end of every instruction the
microprocessor will check for valid interrupt
signal.
If there is no interrupt then the microprocessor
continues with the execution.
Serial Input Data
Serial Input data
8085 Microprocessor has two Serial Input/Output pins
that are used to read/write one bit
data to and from peripheral devices.

SID (Serial Input Data) line


There is an One bit Input line inside the 8085 CPU (Pin
number 5)
1 bit data can be externally read and stored using this
SID line
The data that is read is stored in the A7th bit of the
Accumulator
RIM instruction is used to read the SID line
Serial Output Data
SOD (Serial Output Data) Line
There is a One bit Output port inside the 8085
CPU (Pin number 4
1 bit data can be externally written in this port.
To write data into this port, SIM instruction is
used.
The data that is to be written in this port must
be stored in the A7th bit of the Accumulator.
Bit A6 of the Accumulator is known as SOE
(Serial output Enable). This bit must be set to 1
to enable Serial data output.
Stack
Portion of RAM memory
for temporary storage and
retrieval of data.
Stack is a RAM memory
Stack pointer is a 16 bit
register.
Stack space grows
upward(numerically
decreasing order of
memory address)
PUSH and POP
LIFO Last In First Out
sequence
Direct Memory Access
The I/O device requests the microprocessor for Direct
memory Access(DMA) by sending a signal on a
special pin,the microprocessor disconnects itself from
memory and I/O device by tristating the address,data
and control buses and acknowlege the device by
sending the DMA acknowledge signal.
The I/O device performs the data transfer.On
completion of data transfer the I/O device initmates
the withdrawing the DMA request.
Serial Data Transfer
In serial data transfer,each bit of the word is sent in
succession,one at a time over a single pair of wires.
A parallel to serial coverter is used to convert the
incoming parallel data to a serial form and then the
data is sent out with the least significant bit D0 first
and the most significant bit D7 last.