DIGITAL SIGNAL

PROCESSING
MODULE 4
DSP PROCESSORS : TMS 320
C67x & TMS 320 C54x
 TMS 320 C67x
Introduction
Architecture & Architectural Issues
Addressing Modes
Instruction Set
 INTRODUCTION
TMS 320 C67x family of 32- bit floating
point DSP processors
Architecture : VLIW (Very Large Instruction
Word ) Architecture
Shares similarity with TMS 320 C62x &
TMS 320 C64x DSP processors
Features : High precision , Large dynamic
range , Intensive Computation al ability
Applications : RADAR , SONAR , 3-D
graphics , medical imaging , wireless base
stations & digital scriber loops.
 ARCHITECTURE
REFER FIG ON NEXT SLIDE!!!!!
 On chip memory
Program / data DMA
memory

Program-address bus (32 bit)

Data path 1 address bus (32
bit) To ext add bus (32)
Data path 2 address bus (32
bit)
DMA address bus (32 bit)

Program data bus (256 bit)

Data path 1 data bus ( 64 bit)

Ext data bus (32)
Data path 2 data bus (64 bit)

DMA data bus (32 bit)

.D1 .D2
Register .M1 .M2 Register
file A .L1 .L2 file B
.S1 .S2
Program Control Unit
 ARCHITECTURAL DETAILS
CONSISTS OF
1. PROGRAM CONTROL UNIT (PCU)
2. DIRECT MEMORY ACCESS (DMA)
CONTROLLER
3. ON-CHIP MEMORY
4. PROGRAM & DATA MEMORY
INTERFACES
5. TWO FLOATING POINT DATA PATHS
 OPERATIONS - I
The processor can execute 8 instruct./Clk cycle.
Earlier versions operated with max 167 MHz clk
rate , 1.9V supply for core and 3.3 V for I/O
supply
Modern versions use 100MHz and eliminate on-
chip peripherals to reduce cost.
Time required for floating point arithmetic longer
than single precision arithmetic.
Multiple cycle , double precision floating point
arithmetic restricts usage of cross paths
Thus slower throughput compared with single
precision arithmetic
 OPERATION - II
8 instruct./clk cycle =
1. 2 single precision multiplications OR
2. 1 double precision floating point multiplication
. Besides ,
1. 16X16 bit integer multiplications
2. 32X32 - bit integer multiplications
. Conversion b/w fixed and floating point : using
control registers (rounding) , status bits
(overflow/underflow , divide by zero , not no?)
 DATA PATHS
TWO FLOATING POINT DATA PATHS :DATA PATH 1
& DATA PATH 2
Supports 64-bit data for 32-bit single precision
arithmetic.
Supports 64-bit data for double precision floating
point arithmetic.
Each consists of
1. a set of 4 execution units (.L ,.S , .M ,.D)
2. A GP register file
3. Paths for moving data b/w memory and registers
 Registers :
1. 2 independent register files (A & B)
2. Each contains 16 32 bit GP
Registers
3. Registers used for storing addresses
& data
4. A pair of adjacent registers used to
hold 64-bit data for 64-bit fl.pnt.arith
5. Cross path ( only 1 cross path at a
time )used to transport data b/w
data paths A & B
 BUS STRUCTURE
Allows 64-bit data load
access double precision floating point
operands
Acesss single precision fixed point operands
BUS availability & features:
1. Data path connection to memory requires
32-bit address bus and 64-bit data bus
2. Program memory requires 32-bit address
bus and 256- bit data bus
 MEMORY
On chip memory MODIFIED
HARVARD ARCH.
Separate pgm and data mem.
Spaces
(Latest ver.)- configure on chip
memory as Level-1 (L1) and Level-2
(L2) pgm & data cache
 On chip memory available
PROCESSORS DATA PROGRAM REMARKS
MEMORY MEMORY
C6701 16 K X 32 16K X 32
C6711 32K BITS L1 32K BITS L1 512K BITS
CACHE CACHE UNIFIED L2
CACHE
C6712 32K BITS L1 32K BITS L1 512K BITS
CACHE CACHE UNIFIED L2
CACHE

C6713 4K BYTES L1 4K BYTES L1 64K BYTES L2

CACHE CACHE CACHE
192K BYTES
L2 SRAM
 DMA CONTROLLER
Peripherals and external memory interface
C6701 4 channel DMA
16 BIT HPI
2 BSP s
2 timers
32 bit EMIF
C6711 - 16 channel (ENHANCED) DMA
16 BIT HPI
2 BSP s
2 timers
32 bit EMIF (Ext mem interface)
C6712 - 16 channel enhanced DMA
16 BIT HPI
2 SP s
2 timers
16 bit EMIF
C6713 -16 channel enhanced DMA
16 BIT HPI
2 McBSP s
2 timers
32 bit EMIF
DMA USAGE
 INSTRUCTION SET
INTRO:
Based on VLIW architecture
Architectural similarity with TMS 320 C62X & TMS 320
C64X
C67X instruction set with added floating point
capability is superset of C62X fixed point instruction set
It basically extends C62X instruction set to support
floating point arithmetic
All C62X instructions can run on C67X processor
Upward compatible with C62X proc.
Not compatible with C64X proc. despite similar arch.
ADDED FEATURES :
32 BIT INTEGER MULTIPLY
DOUBLE WORD LOAD
FLOATING POINT ADDITION ,
SUBTRACTION , MULTIPLICATION etc
Detailed
1. Single precision floating point addition
2. Single precision floating point subtraction
3. Single precision floating point absolute value
4. Double precision floating point addition
5. Double precision floating point subtraction
6. Double precision floating point absolute value
7. Single precision floating point multiplication
8. Double precision floating point multiplication
9. 32x32 bit integer multiplication with 64 bit product
10.32x32 bit integer multiplication with 32 bit product
11.Double word load
12.Double word address calculation
13.Single precision floating point compare
14.Double precision floating point compare
15.Single precision floating point reciprocal estimate
16.Double precision floating point reciprocal estimate
17.Single precision floating point reciprocal sq.root
18.Double precision floating point reciprocal sq.root
19.Fixed point to floating point conversion
20.Floating point to fixed point conversion
21.Single precision floating point to double precision floating point conversion
Single precision floating point to double precision floating point conversion
 Some specialities ???
Parallel move capability
Supports 64 bit double word load
( but only 32-bit stores !!!)
 Misgivings!!!!
No bit reversal addressing
No hardware stack- software stack
can be implemented
No hardware looping- looping done
using software