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Chapter 5 MOS Capacitor

MOS: Metal-Oxide-Semiconductor

Vg Vg
gate
metal gate
SiO2 SiO2
N+ N+

Si body P-body

MOS capacitor MOS transistor

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-1
Chapter 5 MOS Capacitor
Ec

Ec
N +polysilicon

P-Silicon body
Ef , Ec Ef
Ev
SiO2

Ev

Gate Si
Body

Ev

This energy-band diagram for Vg = 0 is not the simplest one.


Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-2
5.1 Flat-band Condition and Flat-band Voltage
E0
SiO2 =0.95 eV
Ec
qg
3.1 eV 3.1 eV Si q s = Si + (Ec Ef )
=4.05eV

Ec, Ef Ec
qVfb
Ef
Ev
Ev
N+ -poly-Si 9 eV P-body

The band is flat at


E0 : Vacuum level the flat band voltage.
4.8 eV
E0 Ef : Work function V fb g s
E0 Ec : Electron affinity
Ev
Si/SiO2 energy barrier
SiO2
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-3
5.2 Surface Accumulation
Make Vg < Vfb
3.1eV
Vox Vg V fb s Vox
Ec , Ef
s : surface potential, band
Ev E0 bending
qVg Vox: voltage across the oxide
q s Ec
Ef s is negligible
Ev when is in
the surface
accumulation.
M O S

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-4
5.2 Surface Accumulation
Vox Vg V fb
Vg <Vt
Gausss Law Vox Qacc / Cox

Qacc Cox (Vg V fb )

Vox Qs / Cox

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-5
5.3 Surface Depletion ( Vg > Vfb )

qVox
Ec
gate q s
++++++ --
Ef
SiO - Ev
2 -
-- -- -- -- -- -- -- qVg
V -------
depletion layer Ec, Ef Wdep
depletion
charge, Q dep
region
Ev
P-Si body

M O S

Qs Qdep qN aWdep qN a 2 s s
Vox
Cox Cox Cox Cox

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-6
5.3 Surface Depletion

qN a 2 s s
Vg V fb s Vox V fb s
Cox
This equation can be solved to yield s .

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-7
5.4 Threshold Condition and Threshold Voltage

Threshold (of inversion): Ec


ns = Na , or st
Ei
A C =q
Ef
(EcEf)surface= (Ef Ev)bulk , or D B
Ev
qVg = qVt
Ec, Ef
A=B, and C = D

kT N a Ev
st 2B 2 ln M O S
q ni

Eg kT N v kT N v kT N a
q B ( E f Ev ) |bulk ln ln ln
2 q ni q Na q ni
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-8
Threshold Voltage

Vg Vfb s Vox

At threshold,
kT N a
st 2B 2 ln
q ni
qN a 2 s 2 B
Vox
Cox

qN a 2 s 2B
Vt Vg at threshold V fb 2B
Cox

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-9
Threshold Voltage

Tox = 20nm

V t(V), N + gate/P-body

Vt (V), P+ gate/N-body
Body Doping Density (cm -3 )

qN sub(a)2 s 2 B + for P-body,


Vt V fb 2 B
Cox for N-body
T = 20nm
ox
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-10

ody
ody
5.5 Strong InversionBeyond Threshold
Vg > Vt 2 s 2 B
Wdep Wdmax
qN a

Vg > Vt Ec
-
Ef
--- Ev
gate --
++++++++++ qVg
SiO 2
- - - - - - - -
V - - - - - - - Ec, Ef

Q dep Qinv
Ev
P - Si substrate

M O S

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-11
Inversion Layer Charge, Qinv (C/cm2)

Qdep Qinv qN a 2 s 2B Qinv


Vg V fb 2B V fb 2B
Cox Cox Cox Cox
Qinv
Vt
Cox Qinv Cox (Vg Vt )
Vg > Vt Vg > Vt

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-12
5.5.1 Choice of Vt and Gate Doping Type

Vt is generally set at a small


positive value so that, at Vg =
0, the transistor does not
have an inversion layer and
current does not flow
between the two N+ regions
P-body is normally paired with N+-gate to achieve a small
positive threshold voltage.
N-body is normally paired with P+-gate to achieve a small
negative threshold voltage.

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-13
Review : Basic MOS Capacitor Theory

s

2B

Vg
accumulation Vfb depletion
Vt inversion

Wdep

Wdmax
Wdmax = (2s2 q a

s)1/2

Vg
accumulation Vfb depletion Vt inversion

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-14
Review : Basic MOS Capacitor Theory
Qdep=- qNaWdep
Vfb
accumulation depletion inversion total substrate charge, Qs
(a) Vg
0 Vt
qNaWdep
Qs Qacc Qdep Qinv
qNaWdmax

Qinv Qs
accumulation depletion inversion accumulation depletion inversion
(b) Vg regime regime regime
Vfb Vt
slope = Cox

Vfb
Vg
0 Vt
Qacc

slope = Cox
Qinv
(c)
slope = Cox
Vfb Vt
Vg
accumulation depletion inversion

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-15
5.6 MOS CV Characteristics

dQg
dQs
C
dVg dVg

MOS Capacitor
C-V Meter

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-16
5.6 MOS CV Characteristics
dQgdQs
C
dVg dVg
Qs

accumulation depletion inversion


regime regime regime C
Cox

Vfb
Vg
0 Vt

Qinv

slope = Cox Vg
V Vt
accumulation fb depletion inversion

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-17
CV Characteristics
C
Cox

Vg
accumulation Vfb depletion Vt inversion

1 1 1
In the depletion regime:
C Cox Cdep
1 1 2(Vg V fb )

C 2
Cox qN a s
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-18
Supply of Inversion Charge May be Limited
gate gate
Cox Cox
+++++ ++++ C
- Wdep
- - - - - dep

Accumulation Depletion
P-substrate P-substrate

gate gate
Cox Cox
N+ - - - - - - - - DC - - - - - - - - -

Inversion Cdmax-
- - - -
AC
DC and AC Wdmax
Inversion Wdmax
P-substrate P-substrate

In each case, C = ?
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-19
Capacitor and Transistor CV (or HF and LF CV)

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-20
Quasi-Static CV of MOS Capacitor
C
Cox

Vg
accumulation Vfb depletion Vt inversion

The quasi-static CV is obtained by the application of a slow linear-


ramp voltage (< 0.1V/s) to the gate, while measuring Ig with a very
sensitive DC ammeter. C is calculated from Ig = CdVg/dt. This allows
sufficient time for Qinv to respond to the slow-changing Vg .

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-21
EXAMPLE : CV of MOS Capacitor and Transistor
MOS transistor CV,
C QS CV

Does the QS CV or the HF


capacitor CV apply?
HF capacitor CV

Vg

(1) MOS transistor, 10kHz. (Answer: QS CV).


(2) MOS transistor, 100MHz. (Answer: QS CV).
(3) MOS capacitor, 100MHz. (Answer: HF capacitor CV).
(4) MOS capacitor, 10kHz. (Answer: HF capacitor CV).
(5) MOS capacitor, slow Vg ramp. (Answer: QS CV).
(6) MOS transistor, slow Vg ramp. (Answer: QS CV).

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-22
5.7 Oxide ChargeA Modification to Vfb and Vt
Q ox/Cox

Ef, Ec E c Ef, Ec
+
+ E
Vfb0 + c

Ev E Ev Vfb
f

E v
E f

E v

gate oxide body gate oxide body

(a) (b)

V fb V fb 0 Qox / Cox g s Qox / Cox

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-23
5.7 Oxide ChargeA Modification to Vfb and Vt

Types of oxide charge:

Fixed oxide charge, Si+

Mobile oxide charge, due to Na+contamination

Interface traps, neutral or charged depending on


Vg.

Voltage/temperature stress induced charge and


traps--a reliability issue
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-24
EXAMPLE: Interpret this measured Vfb dependence on oxide
thickness. The gate electrode is N+ poly-silicon.
Vfb
10 nm 20 nm 30 nm
Tox
0

0.15V


0.3V

What does it tell us? Body work function? Doping type? Other?
Solution: V fb g s QoxTox / ox

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-25
from intercept g s 0.15 V

E0 , vacuum level

g s = g + 0.15V

Ef , Ec Ec
Ef

Ev Ev
N+ -Si gate Si body

0.15 eV kT
N-type substrate, N d n N c e 1017 cm -3
from slope Qox 1.7 10 8 C / cm 2

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-26
5.8 Poly-Silicon Gate DepletionEffective
Increase in Tox
Gausss Law Wdpoly oxEox / qN poly
1 1
1 1 Tox Wdpoly
P+ poly-Si C
C
Cpoly ox C poly ox s
Co x ox

P+ ++++++++
P+ Tox Wdpoly / 3

Ec
Ef If Wdpoly= 15 , what is the
N-body
Ev
effective increase in Tox?

(b)
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-27
Effect of Poly-Gate Depletion on Qinv

Qinv Cox (Vg poly Vt )

Wdpoly Poly-gate depletion degrades


Ec MOSFET current and circuit speed.

Ef , E v
How can poly-depletion be
minimized?
q poly

Ec
Ef

Ev
P+ -gate N-substrate

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-28
EXAMPLE : Poly-Silicon Gate Depletion
Vox , the voltage across a 2 nm thin oxide, is 1 V. The P+poly-
gate doping is Npoly = 8 1019 cm-3 and substrate Nd is 1017cm-3.
Find (a) Wdpoly , (b) poly , and (c) Vg .

Solution:
(a) Wdpoly oxEox / qN poly oxVox / Tox qN poly
3.9 8.85 10 14 (F/cm) 1 V


2 10 7cm 1.6 10 19 C 8 10 cm
19 3

1.3 nm

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-29
EXAMPLE : Poly-Silicon Gate Depletion
2 s poly
(b) Wdpoly
qN poly

dpoly qN polyWdpoly
2
/ 2 s 0.11 V

(c) Vg V fb st Vox poly


EgkT N c
V fb ln 1.1 V 0.15 V 0.95 V
q q Nd
Vg 0.95 V 0.85 V 1 V 0.11 V 1.01 V
Is the loss of 0.11 V from the 1.01 V significant?

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-30
5.9 Inversion and Accumulation Charge-Layer
ThicknessQuantum Mechanical Effect
Average inversion-layer location below the Si/SiO2 interface is
called the inversion-layer thickness, Tinv .
Electron Density
poly-Si
Gate depletion SiO2 Tinv Si
region
Quantum
mechanical theory


-50 -40 -30 -20 -10 0 10 20 30 40 50 A
Physical Tox
Effective T o
x
n(x) is determined by Schrodingers eq.,
Poisson eq., and Fermi function.
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-31
Electrical Oxide Thickness, Toxe

Tinv is a function of
the average electric
field in the inversion
layer, which is (Vg +
Vt)/6Tox (Sec. 6.3.1).
Tinv of holes is larger
than that of electrons
because of difference
in effective mass.
Toxe is the electrical
oxide thickness.
Toxe Tox Wdpoly / 3 Tinv / 3 at Vg=Vdd

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-32
Effective Oxide Thickness and Effective
Oxide Capacitance
Qinv Coxe (Vg Vt )
Toxe Tox Wdpoly / 3 Tinv / 3

C
Basic CV
Cox
with poly-depletion

with poly-depletion and


charge-layer thickness

measured data

Vg

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-33
Equivalent circuit in the depletion and the inversion regimes

C p oly
Cox Cox Cp oly
Co x
Co x
Cdep
Cdep Cin v Cdep, min Cinv Cinv

(a) (b) (c) (d)


General case for In the depletion
both depletion and Vg Vt Strong inversion
regions
inversion regions.

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-34
5.10 CCD Imager and CMOS Imager
5.10.1 CCD Imager
Ec -

Ef
--
Ev -

Ec, E f Ec , Ef

Ev Ev

(a) (b)

Deep depletion, Qinv= 0 Exposed to light


Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-35
CCD Charge Transfer
V3
V2
V1
V1 > V2 = V3

oxide
(a) - - - - - - - - - - - - -
depletion region - -

P-Si
V1 V2 V3 V1 V2 V3 V1
V2 > V1 > V3

oxide
- - - - - - - -
(b) depletion region

P-Si

V1 V2 V3 V1 V2 V3 V1
V2 > V1 = V3

oxide
- - - - - - - -
(c) depletion region

P-Si

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-36
two-dimensional CCD imager

Signal out
Reading row,
shielded from light Charge-to-voltage converter

The reading row is shielded from the light by a metal film.


The 2-D charge packets are read row by row.

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-37
5.10.2 CMOS Imager
PN junction
charge
collector CMOS imagers can be
switch integrated with signal
V1 processing and control
circuitries to further
Amplifier reduce system costs.
V2
circuit However, The size
constrain of the sensing
V3 circuits forces the
CMOS imager to use
very simple circuits

Shifter circuit Signal out

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-38
5.11 Chapter Summary
N-type device: N+-polysilicon gate over P-body
P-type device: P+-polysilicon gate over N-body

V fb g s (Qox / Cox )

Vg V fb s Vox poly
V fb s Qs / Cox poly

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-39
5.11 Chapter Summary

st 2 B or ( B 0.45 V)
kT N sub
B ln
q ni

qN sub 2 s | st |
Vt V fb st
Cox
+ : N-type device, : P-type device

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-40
A c c u m u l a ti o n
V g < V fb < 0 F la t-b a n d V g > V fb > 0
E f V g = V fb< 0 V g = V fb > 0
Ef
5.11 Chapter Summary Ef
Ef
N-type Device EE ff P-type Device
EE ff
(N+-gate over P-substrate) (P+-gate over N-substrate)
F la t-b a n d
V g = V fb < 0 D ep letio n V g = V fb > 0
Ef Ef
V g 0 > V fb V g 0 < V fb
Ef Ef
Ef Ef
Ef Ef

D ep letio n
V g 0 > V fb V g 0 < V fb
T h r e s h o ld Vg=Vt<0
E f V g = V t> 0 Ef
Ef Ef Ef
Ef
Ef
Ef

T h r e s h o ld
Whats the diagram like at V > VVg = tV<?t < 0 at Vg= 0?
V g = V t> 0
I n v e r si o n g
V g > V t> 0 Ef Vg Vt
Ef E
f
Modern Semiconductor Devices for Integrated
E f Circuits (C. Hu) Slide 5-41
Ef Ef
5.11 Chapter Summary
N-type Device P-type Device
(N +-gate over P-substrate) (P +-gate over N-substrate)

QS CV
Transistor CV

Capacitor
(HF) CV

Vg Vg

What is the root cause of the low C in the HF CV branch?

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-42

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