Академический Документы
Профессиональный Документы
Культура Документы
Peripherals
Module I
3 12/07/21
8255 – Programmable Peripheral Interface
4 12/07/21
8255 – Programmable Peripheral Interface
Pin Details
5 12/07/21
8255 – Programmable Peripheral Interface
www.lectnote.blogspot.com
6 Figure 1.1 12/07/21
8255 – Programmable Peripheral Interface
Modes
Bit Set/Reset(BSR) Mode
Set/Reset bits in Port C
I/O Mode
Mode 0
Mode 1(Handshake mode)
Mode 2
7 12/07/21
8255 – Programmable Peripheral Interface
Block Diagram
8 12/07/21
8255 – Programmable Peripheral Interface
Control Logic
RD(Read)
Reads data from I/O Port of 8255 to Microprocessor
WR(Write)
MPU writes into a selected I/O Port or Control Register
RESET(Reset)
Clears the Control Register&Sets all ports in input mode
CS, A0, A1
Device select Signals
9 12/07/21
8255 – Programmable Peripheral Interface
10 12/07/21
8255 – Programmable Peripheral Interface
Control Word
Contents of Control Register :- Control Word
This register is used to write control word when A1 &
A0 at logic 1
Not accessible for a read operation
11 12/07/21
8255 – Programmable Peripheral Interface
12 12/07/21
8255 – Programmable Peripheral Interface
13 12/07/21
8255 – Programmable Peripheral Interface
0/1
Modes of operation
I/O Mode
Mode 0: Simple Input or Output
Ports A and B are used as Simple I/O Ports
Port C as two 4-bit ports
Features
Outputs are latched
Inputs are not latched
Ports do not have handshake or interrupt capability
15 12/07/21
8255 – Programmable Peripheral Interface
Modes of operation
I/O Mode
Mode 1: Input or Output with Handshake
Handshake signals are exchanged between MPU & Peripherals
Features
Ports A and B are used as Simple I/O Ports
Each port uses 3 lines from Port C as handshake signals
Input & Output data are latched
interrupt logic supported
16 12/07/21
8255 – Programmable Peripheral Interface
Modes of operation
I/O Mode
Mode 2: Bidirectional Data Transfer
Used primarily in applications such as data transfer between two
computers
Features
Ports A can be configured as the bidirectional Port
Port B in Mode 0 or Mode 1.
Port A uses 5 Signals from Port C as handshake signals for data
transfer
Remaining 3 Signals from Port C Used as – Simple I/O or
handshake for Port B
17 12/07/21
8255 – Programmable Peripheral Interface
Modes of operation
BSR(Bit Set/Reset) Mode
Concerned only with the 8-bits of Port C.
Set or Reset by control word
Ports A and B are not affected
18 12/07/21
Serial Data Communication
Serial Data Format
The serial data format includes
one start bit,
five or eight data bits,
one stop bit.
A parity bit and an additional stop bit might be
included in the format as well.
19 12/07/21
Methods of Data Communication
Modes of data transmission
Simplex
Data is transmitted only in one direction over a single
communication channel.
Duplex
Data may be transferred between two transivers in both
directions simultaneously.
Half Duplex
Data transmission may take place in either direction, but
at a time data may be transmitted only in one direction
20 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
21 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
22 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
Block Diagram
23 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
Five Sections
Read/Write Control Logic
Interfaces the chip with MPU
Determine the functions according to the control word
Monitors data flow
Transmitter
Converts parallel word received from MPU into serial bits
Transmits serial bits over TXD line to a peripheral.
Receiver
Receives serial bits from peripheral
Converts serial bits into parallel word
Transfers the parallel word to the MPU
Data Bus Buffer
Modem Controller
Used to establish data communication modems over telephone line
24 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
25 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
Input Signals
CS – Chip Select
When this signal goes low, 8251 is selected by MPU for
communication
C/D – Control/Data
When this signal is high, the control register or status
register is addressed
When it is low, the data buffer is addressed
Control and Status register is differentiated by WR and
RD signals, respectively
26 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
WR – Write
Either writes in the control register or sends outputs to
the data buffer.
This connected to IOW or MEMW
RD – Read
Either reads a status from status register or accepts data
from the data buffer
This is connected to either IOR or MEMR
RESET - Reset
CLK - Clock
Connected to system clock
Necessary for communication with microprocessor.
27 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
CS C/D RD WR Function
0 1 1 0 MPU writes instruction in the control register
0 1 0 1 MPU reads status from the status register
0 0 1 0 MPU outputs the data to the Data Buffer
0 0 0 1 MPU accepts data from the Data Buffer
1 X X X USART is not Selected
28 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
Control Register
16-bit register
First byte is called mode instruction
Second byte is called command instruction
This register can be accessed an output port when the
C/D pin is high
Status Register
Checks ready status of a peripheral
Data Buffer
29 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
Transmitter Section
Accepts parallel data and converts it into serial data
Two registers
Buffer Register
To hold eight bits
Output Register
Converts eight bits into a stream of serial bits
Transmits data on TxD pin with appropriate framing
bits(Start and Stop)
31 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
Signals Associated with Transmitter Section
32 December 7, 2021
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
Receiver Section
33 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
34 12/07/21
8251 – UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER
35 12/07/21
8279 – Programmable Keyboard/Display
Interface
36 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
37 12/07/21
38 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
I/O Control
The I/O control section controls the flow of data to/from
the 8279
Data Buffers
The data buffers interface the external bus of the system
with internal bus of 8279.
The I/O section is enabled only if CS is low.
The pins A0,RD and WR select the command, status
or data read/write operations carried out by the CPU
with 8279.
39 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
40 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
Scan Counter
has two modes to scan the key matrix and refresh the display
Encoded Mode
the counter provides binary count that is to be externally
decoded to provide the scan lines for keyboard and display
Decoded Mode
the counter internally decodes the least significant 2 bits and
provides a decoded 1 out of 4 scan on SL0-SL3
The keyboard and display both are in the same mode at a
time.
41 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
42 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
43 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
44 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
45 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
46 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
47 12/07/21
8279 – PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
Keyboard Modes
Scanned Keyboard mode with 2 Key Lockout
Scanned Keyboard with N-Key Rollover
Scanned keyboard special error mode
Sensor matrix mode
Display Modes
Left Entry mode(Type writer mode)
Right Entry mode(Calculator mode)
48 12/07/21
Module II
50 12/07/21
51 12/07/21
Interfacing Matrix keyboard
Steps
52 12/07/21
Program
Check whether all keys are open
Necessary to avoid misinterpretation if a key is held for a long
time
Check a key closure
D3-D0 should be 1111
Identify the key
Complex procedure
Grounding one row at a time and checking each column for zero
Find the binary key code for the key
Counter Procedure
For 5 Rows counter is incremented from 0 to 13H
53 12/07/21
Interfacing Key Board Hardware
Approach
54 12/07/21
Interfacing circuit of a six – seven- segment LED display
using the technique of multiplexing.
55 12/07/21
4x4 MATRIX KEYBOARD & 4 DIGIT 7 SEGMENT DISPLAY
INTERFACE
56 12/07/21
FLOWCHARTS
Source Program and Interrupt Service Routine
57 12/07/21
Source program:
58 12/07/21
Interrupt service routine
59 12/07/21
Digital-To-Analog(D/A) Converters
60 12/07/21
Interfacing AD558 with 8085
61 12/07/21
Interfacing a 10-bit D/A Converter
In many D/A converter application 10-bit or 12-bit is
required.
The 8-bit microprocessor has only 8-bit data lines.
To transfer 10-bits, the data bus is time-shared by
using two output ports: one for first 8-bit and second
for remaining two bits.
AD7522 is a CMOS 10-bit D/A converter with an
input buffer and a holding register.
The ten bits are loaded into the input register in two
steps using two output ports.
62 12/07/21
Interfacing a 10-bit D/A Converter
The low-order eight bits are loaded with the control
line LBS and the remaining two bits are loaded with
HBS.
Then all ten bits are switched into a holding register
for conversion by enabling the line LDAC.
63 12/07/21
Interfacing a 10-bit D/A Converter
64 12/07/21
Analog-To-Digital(A/D) converter
65 12/07/21
Interfacing 8-bit A/D Converters
66 12/07/21
Interfacing 8-bit A/D Converters
A pulse to START pin begins the conversion process
and disables the tri-state output buffer.
At the end of the conversion period DATA READY
becomes active and the digital output is made available
at the out put buffer.
To interface an A/D converter with the
microprocessor, the microprocessor should
1.Send a pulse to START pin. This can be derived from
a control signal such as Write(WR).
67 12/07/21
Interfacing 8-bit A/D Converters
2. Wait until the end of conversion. The end of
conversion period can be verified either by status
checking(Polling) or by interrupt.
3. Read the digital signal at an input port.
68 12/07/21
69 12/07/21