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In this lecture
Introduction
ARM Programmers Model
ARM Instruction Set
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ARM Ltd
Founded in November 1990
Spun out of Acorn Computers
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Introduction
Many devices are powered by ARM processors
E.g.
Samsung galaxy S4 ----- ARM Cortex-A15/Cortex-A7
IPhone 4 -------- ARM Cortex-A8
Ipad mini ------- ARM Cortex-A9
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Introductioncntd
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ARM Versions
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ARM Core Block Diagram
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ARM Registers
General-purpose registers
37 32-bit registers
At any one time only 16 of these registers are visible (r0 r15)
Some of these registers have special functions
Register r13 is used as stack pointer (sp)
Register r14 is called the link register (lr) and is where the core puts
the return address whenever it calls a subroutine
Register r15 is the program counter (pc) and contains the address of
the next instruction
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ARM Processor Modes
ARM has seven basic operating modes
Each mode has access to its own stack space and a different subset
of registers
Some operations can only be carried out in a privileged mode
Mode Description
Supervisor Entered on reset and when a Supervisor call
(SVC) instruction (SVC) is executed
Exception modes
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The ARM Register Set
User mode IRQ FIQ Undef Abort SVC
r0
r1 ARM has 37 registers, all 32-bits long
r2
r3
A subset of these registers is accessible in
each mode
r4
r5 Note: System mode uses the User mode
register set.
r6
r7 SPSR registers are used to save CPSR
r8 r8 of previous mode
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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CPSR Register
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ARM Exceptions
Exception
Any condition that needs to halt the normal sequential execution of
instructions
Five types of exceptions in ARM
Each exception changes the processor mode
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Exception Handling
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ARM Instruction Set
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Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.
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Program Counter (r15)
When the processor is executing in ARM state:
All instructions are 32 bits wide
All instructions must be word aligned
Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction
cannot be halfword or byte aligned)
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Instruction Set
Different types of instructions
Data processing instructions
Load-store instructions
Branch instructions
Software interrupt instruction
Program status register instructions
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Data Processing Instructions
Consist of :
Arithmetic: ADD ADC SUB SBC RSB RSC
Logical: AND ORR EOR BIC
Comparisons: CMP CMN TST TEQ
Data movement: MOV MVN
By default, data processing instructions do not affect the condition code flags but
the flags can be optionally set by using S. CMP does not need S.
loop
SUBS r1,r1,#1 decrement r1 and set flags
BNE loop if Z flag clear then branch
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Condition Codes
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Conditional Execution Examples
5 instructions 3 instructions
5 words 3 words
5 or 6 cycles 3 cycles
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More Examples
Use a sequence of several conditional instructions
if (a==0) func(1);
CMP r0,#0
MOVEQ r0,#1
BLEQ func
Set the flags, then use various condition codes
if (a==0) x=0;
if (a>0) x=1;
CMP r0,#0
MOVEQ r1,#0
MOVGT r1,#1
Use conditional compare instructions
if (a==4 || a==10) x=0;
CMP r0,#4
CMPNE r0,#10
MOVEQ r1,#0
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The Barrel Shifter
LSL : Logical Left Shift ASR: Arithmetic Right Shift
CF Destination 0 Destination CF
Destination CF
e.g.
MOV r0,r1,LSL#2 (r0 = r1*4)
ADD r0, r1, r1, LSL#3 (r0 = r1+r1*8 = 9*r1)
ALU
Result
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More Readings
ARM System Developers Guide (chapters 2 & 3)
ARM Architecture Reference Manual
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