Motorolla MC 68000

Muntasir Shamim 142407

Sakib Mahtab 142408
Arnob Sadaf 142409
Motorola MC68000
MC68000 is Motorolas first 16 bit microprocessor.
Address and data registers are 32 bits wide
ALU is 16 bits wide
Maximum Internal Clock frequency is 25Mhz
whilst it can also operate on 6,8,10,12,16.67 Mhz
68000 is packaged in a 64 bit DIP(dual in line package)
Internal Architecture of a microprocessor
Block Diagram of Motorolla 68000
Comparison of Motorola 68XXX
Specialty of m68k family
16 32-Bit Data and Address Registers
16-Mbyte Direct Addressing Range
Program Counter
6 Powerful Instruction Types
Operations on Five Main Data Types
Memory-Mapped Input/Output (I/O)
14 Addressing Modes
Address bus
Address storage and computation uses 32 bits internally; however,
the 8 high-order address bits are ignored due to the physical lack of
device pins. This allows it to run software written for a logically flat
32-bit address space, while accessing only a 24-bit physical address
space.
Motorola's intent with the internal 32-bit address space was forward
compatibility, making it feasible to write 68000 software that would
take full advantage of later 32-bit implementations of the 68000
instruction set
Internal Registers

8 data registers (D0-D7)

8 address registers (A0-A7)

There are 2 A7 registers
User Stack Pointer (USP)
Supervisor Stack Pointer (SSP)

Program Counter (PC)

The PC contains the address of the instruction
currently executing. During instruction
execution and exception processing, the
processor automatically increments the contents
or places a new value in the PC.
Status/Condition Code Register
Data Organization in Memory
Bytes are individually addressable
High-order byte has same address a word
Low-order byte has odd address, one count higher.
Instructions and multibyte data accessed only on
word (even byte) boundaries.
If a long-word operand is located at address n
(n even), then the second word of that operand
is located at address n+2.
Data types supported by M68000:
bit data; integer data of 8, 16, and
32 bits; 32-bit addresses; binary-coded-decimal data
Input/output
INSTRUCTIUON SET

Instruction format is
<label> opcode<.field> <operands> <;comments>
where
<label> pointer to the instructions memory location
opcode operation code (i.e., MOVE, ADD)
<.field> defines width of operands (B,W,L)
<operands> data used in the operation
<;comments> for program documentation
Data movement instructions
Arithmatic Instruction
Addressing Modes
Data Register Direct Mode
In the data register direct mode, the effective address field specifies
the data register containing the operand.

Address Register Direct Mode

In the address register direct mode, the effective address field
specifies the address register
containing the operand.
 Address Register Indirect Mode
In the address register indirect mode, the operand is in memory. The
effective address field
specifies the address register containing the address of the operand
in memory
Genearation : Ea=(An)
 Address Register Indirect with Displacement Mode
In the address register indirect with displacement mode, the operand is in memory. The sum
of the address in the address register, which the effective address specifies, plus the signextended
16-bit displacement integer in the extension word is the operands address in
memory. Displacements are always sign-extended to 32 bits prior to being used in effective
address calculations.
Address Register Indirect with Index (8-Bit
Displacement) Mode

Clock Timing Specifications

Of a 68000
 Division Of Signals

1.Synchronous and asynchronous control lines

2.System control lines
3.Interrupt control lines
4.DMA control lines
5.Status lines
 Synchronous and Asynchronous
Control Lines

*Bus control is asynchronous, a signal needs to be sent back to complete a cycle

*In synchronous operation , bus control is clocked using a common system clock

signal

*All READ and WRITE control must be synced with it

*In asynchronous control , this is not required.

 To transfer data over bus

*Pins required:

*E (Enable) : The E clock is output at a frequency that is one-tenth of the 68000 input
clock.
*VPA' (Valid Peripheral Address) : VPA is an input and tells the 68000 that a 6800 device
is being addressed and therefore that data transfer must be synchronized with the E
clock.
*VMA (Valid Memory Address) : VMA is the processors response to VPA

*AS' (Address Strobe) : LOW when the address on the address bus is valid.
 Peripheral Interfacing Sequence

1. 68000 initiates a cycle by starting a normal R/W cycle

2. 6800 peripheral defines the 68000 cycle by asserting the VPA input
*If VPA' is asserted as soon as possible after AS', then VPA' will be recognized as
being asserted after 3 cycles.
*If not it inserts wait states until VPA' is recognized by 68000
3.68000 monitors E until its LOW. Then it syncs all R/W with E. VMA' is asserted low.
4.6800 waits until E is HIGH and then transfers data
5.68000 waits until E goes LOW, terminates the cycle, initiates a new one.
 To control address and data transfer asynchronously

AS : 1. Outputs notify Peripheral device to transfer data

2. A part of address decoding scheme
3. Required address is generated on the address bus.
R/W : Reads or Writes.
DTACK (Data Knowledge) : Informs about a transfer.
UDS'(Upper Data Strobe) : When asserted the contents of even addresses are transferred on the high-
order eight lines of the data bus, D8-D15.
LDS'(Lower Data Strobe) : When asserted the contents of odd addresses are transferred on the low-
order eight lines of the data bus, D0-D7.
 System Control Lines

BERR (Bus Error) : Error in instruction, if not received DTACK.

HALT' : When activated, 68000 completes current instruction and goes to a high
impedance state until it is returned to HIGH.
RESET': Must be low with HALT' for 10 clock cycles.

Interrupt Control Lines

IPL0'
IPL1'
IPL2'

**(111 means no interrupt,000 means interrupt with highest priority)

 Status Lines
FC2
FC1
FC0

*tells external devices whether user data or supervisor data is addressed

*can be used to partition 4 functional areas: user data memory, user program memory,
supervisor data memory, supervisor program memory
*helps in multitasking
 DMA Control Lines

BR'(Bus request): is an input to the 68000

BG'(Bus Grant): output line will be activated one clock pulse after BR'
BGACK'(Bus Grant Acknowledge): After taking over the bus , the external device
must enable the BGACK' line.

Read and Write cycle diagrams

*Uses handshaking mechanism to transfer data between processors and

peripherals
*When A0 address is even,68000 asserts UDS' and reads data via D8-D15 pins
*When A0 is odd, LDS' and reads via D0-D7
 Memory Interface

*68000 can easily be interfaced to memory chips with various speeds

68000 Programmed I/O

*68000 uses a memory mapped I/O

*Data transfer can be done in these ways:
**Interfacing it with a slow 6800 I/O chip , such as the 6821
**Interfacing it with its own family of I/O chips , such as the
68230
 Interrupt System

External Interrupts: The 68000 provides seven levels of external interrupts, 1

through 7. The external hardware provides an interrupt level using the pins IPL0,
IPL1, and IPL2.

Internal Interrupts: The internal interrupt is a software interrupt. This interrupt is

generated when the 68000 executes a software interrupt instruction (TRAP) or by
some undesirable events such as division by zero or execution of an illegal
instruction.

Exception Handling
Group 0 Reset (the highest level in this group), address error (the next level), and
bus error (the lowest level)
Group 1 Trace (the highest level), interrupt (the next level), illegal op-code (next
level), and privilege violation (the lowest level)
Group2 TRAP, TRAPV, CHK, and ZERO DIVIDE (no individual priorities assigned in
group 2)