Introduction to VLSI Testing

Kuen-Jong Lee

Dept. of Electrical Engineering

National Cheng-Kung University
Tainan, Taiwan

V LSI Testing C lass

 Problems to Think

How are you going to test

A 32 bit adder

A 32 bit counter

A 32Mb cache memory

A 107-transistor CPU

A 109-transistor SOC

VLSI Testing Introduction.2 NCKUEE-KJLEE

 OUTLINE
Introduction
Fault modeling
Fault simulation
Test generation
Automatic test pattern generation
(ATPG)
Design for testability
Built-in self test
Synthesis for testability
An example

VLSI Testing Introduction.3 NCKUEE-KJLEE

 Basic Concept of Testing
Testing: To tell whether a circuit is good or bad
VDD

0 0
0
0 0 0/1

Related fields
Verification: To verify the correctness of a
design
Diagnosis: To tell the faulty site
Reliability: To tell whether a good system will work
correctly or not after some time.
Debug: To find the faulty site and try to eliminate the fault
VLSI Testing Introduction.4 NCKUEE-KJLEE
 Why Studying Testing?
Economics!
Reduce test cost (enhance profit)
Automatic test equipment (ATE) is extremely
expensive
Shorten time-to-market
Market dominating or sharing
Guarantee IC quality and reliability
Defects detected in Cost
Rule of Ten: Wafer 0.01 0.1
Cost to detect faulty Packaged chip 0.1 1
IC increases by an Board 1 10
order of magnitude System 10 100
Field 100 1000
VLSI Testing Introduction.5 NCKUEE-KJLEE
 Principle of Testing
Input Patterns Output Response
-1011 Circuit 1-001
11-00 under 0011-
-0-1- -1101
01--0 Test 1001-
0-101 (CUT) 01-11

Stored
Correct Comparator
Response
Test Result
Testing typically consists of
Applying set of test stimuli (input patterns, test vectors)
to inputs of circuit under test (CUT), and
Analyzing output responses
The quality of the tested circuits will depend upon
the thoroughness of the test vectors
VLSI Testing Introduction.6 NCKUEE-KJLEE
 Importance of testing

N = # transistors in a chip
p = prob. (a transistor is faulty)
Pf = prob. (the chip is faulty)

Pf = 1- (1- p) N

If p = 10-6
N = 106

Pf = 63.2%

VLSI Testing Introduction.7 NCKUEE-KJLEE

 Introduction
Integrated Circuits (ICs) have
grown in size and complexity
since the late 1950s
Small Scale Integration (SSI)
Medium Scale Integration (MSI)
Large Scale Integration (LSI)
Very Large Scale Integration
(VLSI)
VLSI
Moores Law: scale of ICs
doubles every 18 months S
M LSI
S S
Growing size and complexity I I
poses many and new testing
challenges

VLSI Testing Introduction.8 NCKUEE-KJLEE

 Importance of Testing
Moores Law results from decreasing feature
size (dimensions)
from 10s of m to 10s of nm for transistors and
interconnecting wires
Operating frequencies have increased from
100KHz to several GHz
Decreasing feature size increases probability
of defects during manufacturing process
A single faulty transistor or wire results in faulty IC
Testing required to guarantee fault-free products

VLSI Testing Introduction.9 NCKUEE-KJLEE

 Difficulties in Testing
Fault may occur anytime
- Design
- Process
- Package
- Field
Fault may occur at any place
Vdd

Vss

VLSI circuit are large

- Most problems encountered in testing are NP-complete
I/O access is limited

VLSI Testing Introduction.10 NCKUEE-KJLEE

 How to do testing

From designers point of view:

Circuit modeling Modeling
Fault modeling

Logic simulation
Fault simulation ATPG
Test generation

Design for test Testable design

Built-in self test

Synthesis for testability

VLSI Testing Introduction.11 NCKUEE-KJLEE
 Circuit Modeling
Functional model--- logic function
- f(x1,x2,...)=...
- Truth table

Behavioral model--- functional + timing

- f(x1,x2,...)=... , Delay = 10

Structural model--- collection of

interconnected components or elements
A E
B 1
0
G
1
C 0
D F
0

VLSI Testing Introduction.12 NCKUEE-KJLEE

 Levels of Structural Description

Circuit level Switch level

VDD VDD VDD
C

C C
4 1
B
C3 C2

Gate level
A E Higher/ System level
B
G

C
D F

VLSI Testing Introduction.13 NCKUEE-KJLEE

 Fault Modeling
The effects of physical defects
Most commonly used fault model: Single stuck-at
fault

A E
A s-a-1 B s-a-1 C s-a-1 D s-a-1
B A s-a-0 B s-a-0 C s-a-0 D s-a-0
G
E s-a-1 F s-a-1 G s-a-1
C E s-a-0 F s-a-0 G s-a-0
D F
14 faults
Other fault models:
- Break faults, Bridging faults, Transistor stuck-open faults,
Transistor stuck-on faults, Delay faults

VLSI Testing Introduction.14 NCKUEE-KJLEE

 Fault Coverage (FC)
# faults detected
FC =
# faults in fault list
Example:
a 1
0
c1 6 stuck-at faults
0 ( a0,a1,b0,b1,c0,c1 )
b 1
0

Test faults detected FC

{(0,0)} c1 16.67%
{(0,1)} a1,c1 33.33%
{(1,1)} a0,b0,c0 50.00%
{(0,0),(1,1)} a0,b0,c0,c1 66.67%
{(1,0),(0,1),(1,1)} all 100.00%

VLSI Testing Introduction.15 NCKUEE-KJLEE

 Wafer Yield (Chip Yield, Yield)
Good Chip

Faulty Chip

Defects

Wafer

Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77

VLSI Testing Introduction.16 NCKUEE-KJLEE

 Testing and Quality

Shipped Parts
IC
Testing
Fabrication
Yield: Quality:
Fraction of Defective parts
good parts per million (DPM)
Rejects

Quality of shipped parts is a function of yield

Y and the test (fault) coverage T
Defect level (DL, reject rate in textbook):
fraction of shipped parts that are defective

VLSI Testing Introduction.17 NCKUEE-KJLEE

 Defect Level, Yield & Fault Coverage
DL: defect level
DL
= 1 - Y (1-T) Y: yield
T: fault coverage

Yield (Y) Fault Coverage (T) DPM (DL)

50% 90% 67,000
75% 90% 28,000
90% 90% 10,000
95% 90% 5,000
99% 90% 1,000
90% 90% 10,000
90% 95% 5,000
90% 99% 1,000
90% 99.9% 100

VLSI Testing Introduction.18 NCKUEE-KJLEE

 Logic simulation
To determine how a good circuit should work

Given input vectors, determine the normal

circuit response

A I C

A D B C
CC

CC
IR

1
2
B F
G
B RB
F IF
E CD C
C E E
JE

H
D E

VLSI Testing Introduction.19 NCKUEE-KJLEE

 Fault simulation

To determine the behavior of faulty circuits

E s.a.0
A 1
0 1/0
1
B 1/0
1
G
0
C F
1
0
D

Given a test vector, determine all faults that

are detected by this test vector.
Example:
1 Test vector (1 1) detects
A 0
C { a0 , b0 , c 1 }
B 1

VLSI Testing Introduction.20 NCKUEE-KJLEE

 Test generation
Given a fault, identify a test to detect this fault
Example: A
1
0 1/0
D
1 1/0
B F
1
C E
0
To detect D s-a-0, D must be set to 1.
Thus A=B=1.
To propagate fault effect to the primary output
E must be 1. Thus C must be 0.
Test vector: A=1, B=1, C=0

VLSI Testing Introduction.21 NCKUEE-KJLEE

 Automatic Test Pattern Generation
ATPG: Given a circuit, identify a set of test vectors
to detect all faults under consideration.
Input circuit

Form fault list

No
More faults? Exit

Yes
Select a fault
Fault
dropping
Test generation

Fault simulation

VLSI Testing Introduction.22 NCKUEE-KJLEE

 Difficulties in Test Generation

1. Reconvergent fanout

A 0/1 Cannot detect the fault

0 s-a-1
D 1
B 1 0 F
0/1
1 1 Fault detected
C 0E

VLSI Testing Introduction.23 NCKUEE-KJLEE

 Difficulties in Test Generation (cont.)

2. Sequential test generation

Combinational part
PIs POs

Y J
K
Y CK clk

VLSI Testing Introduction.24 NCKUEE-KJLEE

 Testable Design
Design for testability (DFT)
ad hoc techniques
Scan design
Boundary Scan

Built-In Self Test (BIST)

Random number generator (RNG)
Signature Analyzer (SA)

Synthesis for Testability

VLSI Testing Introduction.25 NCKUEE-KJLEE

 Example of ad hoc Techniques

Insert test points

MUX

T/N

VLSI Testing Introduction.26 NCKUEE-KJLEE

 Scan Design
Original design Modified design

PIs POs PIs POs

Combinational Combinational
logic logic

SO
FF SFF

FF SFF

FF SFF
T/N
VLSI Testing Introduction.27 SI NCKUEE-KJLEE
 Scan Cell Design

Q DI Q,SO
DI D Q D Q
SI
CK CK
N/T
(SE)

Q Q,SO
DI DI
F
F
SI

F FT F + FT
Most cell libraries now have scan cells!

VLSI Testing Introduction.28 NCKUEE-KJLEE

 Scan Register

Combinational
Circuits

Q D Q D Q D Q D

SO SI SI SI SI

SE
CLK

VLSI Testing Introduction.29 NCKUEE-KJLEE

 Boundary Scan
I/O Pad Boundary scan cell Boundary scan path

TRST*

TDI APPLICATION LOGIC

Sout
Misc. registers
TMS
Instruction register
T
TCK A BIST register
P Bypass register
M Scan register
TDO U Sin
X
TRST*:Test rest (Optional)
TDI: Test data input
TD0: Test data output
TCK: Test clock
TMS: Test mode select

VLSI Testing Introduction.30 NCKUEE-KJLEE

 Boundary Scan (Cont.)

TRST* TRST*

TDI Sout APPLICATION LOGIC TDI Sout APPLICATION LOGIC

Misc. registers Misc. registers

TMS TMS
Instruction register Instruction register
T T
A A
BIST register BIST register
P P
TCK Bypass register TCK Bypass register
Scan register Scan register
M M
U Sin U Sin
TDO X TDO X

TRST* TRST*

TDI APPLICATION LOGIC TDI Sout APPLICATION LOGIC

Sout
Misc. registers Misc. registers
TMS TMS
Instruction register Instruction register
T T
A A BIST register
BIST register P
P Bypass register
TCK Bypass register TCK
Scan register M
Scan register
M
U Sin U Sin
X TDO X
TDO

VLSI Testing Introduction.31 NCKUEE-KJLEE

 Built-In-Self Test (BIST)

Places the job of device testing inside the device

itself
Generates its own stimulus and analyzes its own
response

from system circuit to system

mux
under test

Response
generator

Analyzer
pattern

BIST good/fail
Controller

biston bistdone
VLSI Testing Introduction.32 NCKUEE-KJLEE
 Built-In-Self Test (BIST) (Cont.)

Two major tasks

- Test pattern generation
- Test result compaction
Usually implemented by linear feedback
shift register

F/F F/F F/F

VLSI Testing Introduction.33 NCKUEE-KJLEE

 Random Number Generator (RNG)

0001 0110 1111

1000 1011 0111
0100 0101 0011
F/F F/F F/F F/F
0010 1010 0001
1001 1101 (repeat)
1100 1110

1. Generate pseudo random patterns

2. Period is 2n - 1

VLSI Testing Introduction.34 NCKUEE-KJLEE

 Signature Analyzer (SA)

Input sequence 10101111 (8 bits) 1 2 3 4 5

+ + + Z
G x 1 x 2 x 4 x 5 x 6 x 7 P x 1 x 2 x 4 x 5
Time Input stream Register contents Output stream
0 10101111 00000 Initial state
1 1010111 10000
. . .
. . .
5 101 01111
6 10 00010 1
7 1 00001 01
8 00101 101

Remainder Quotient

R x x 2 x 4 1 x2
VLSI Testing Introduction.35 NCKUEE-KJLEE
 Signature Analyzer (SA) (cont.)
A LFSR performs polynomial division
P x : x 5 x 4 x 2 1
Q x : x 2 1
x7 x6 x 4 x 2 x5 x 4 x 2 1
x x x 1
7 6 5

Px Qx Rx x 7 x 6 x5 x 4 x 2 1 Gx

Probability of aliasing error = 1/2n (n: # of FFs)

VLSI Testing Introduction.36 NCKUEE-KJLEE

 Memory BIST Architecture

Before After

sys_di
sys_addr data
di
sys_wen
clk
data hold_l Memory q
addr Memory
Module rst_l Module
test_h
wen si so
se

VLSI Testing Introduction.37 NCKUEE-KJLEE

 Memory BIST Architecture (Cont.)

sys_addr

Pattern Generator
Algorithm-Based
di
sys_d addr Memory data
isys_wen wen
Module
rst_l

Compressor
clk q
compress_h clk
hold_l
rst
test_h si so
se

BIST Circuitry

VLSI Testing Introduction.38 NCKUEE-KJLEE

 CPU Test Control Architecture
Scan_i
Scan_o
Scan path
Scan_en

logic

rst_l
clk
Bist Memory
hold_l
control
test_h

bist_se
compressor bist_so TDO
bist
decoder
int_scan mbist
scan
decoder
decoder
TDI

TCK IR
TAP Controller
TMS

VLSI Testing Introduction.39 NCKUEE-KJLEE

 Problems re-thinking

A 32-bit adder --- ATPG

A 32-bit counter --- Design for testability + ATPG

A 32MB Cache memory --- BIST

A 107-transistor CPU --- All test techniques

An SOC

VLSI Testing Introduction.40 NCKUEE-KJLEE

 Conclusions
Testing is becoming a major factor in design optimization
Conventionally, the designer often optimize one of the three
attributes: speed, area, and power.
At present, a fourth attribute is considered: Testability.
Two major fields in testing
ATPG
--- Fault simulation
--- Test generation
Testable design
--- Design for testability
--- Built-in self-test
--- Synthesis for testability

VLSI Testing Introduction.41 NCKUEE-KJLEE