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After the initial delay for completing the first task, other tasks
can be completed in time equal to that of the processor that
takes the maximum time to complete its portion of the task.
Most modern processors use some type of linear synchronous
pipeline with added features such as data forwarding and
branch prediction.
When the processor in stage P of the cascade gets the input from
stage P-1, it sends an acknowledgement, which indicates that it
has accepted the input.
External inputs (operands) are fed into the pipeline at the first
stage Si. The processed results are passed from stage Si to
stage Si+1, for all i=1,2,,k-1.
The final result emerges at the last stage, Sk. Each result is
passed to the next stage based upon the clock cycle of the
pipeline. Ideally, we expect the clock pulses to arrive at all the
stages at the same time.