EE466: VLSI Design

Lecture 02
Non Ideal Effects in MOSFETs
 Outline
Junction Capacitances
Parasitic capacitances
Velocity Saturation
Channel length modulation
Threshold Voltage
Body effect
Subthreshold conduction
Junction Capacitances
The n+ regions forms a number of
planar pn-junctions with the
surrounding p-type substrate
numbered 1-5 on the diagram.
Planar junctions 2, 3 and 4 are
surrounded by the p+ channel stop
implant.
Planar junction 1 is facing the
channel while the bottom planar
junction 5 is facing the p-type
substrate with doping NA.
The junction types will be n+/p,
n+/p+, n+/p+ n+/p+ and n+/p.
 Junction Capacitances
The voltage dependent
source-substrate and drain-
substrate junction Vgs = 0 Vgd
capacitances are due to + g +
- -
depletion charge s d
surrounding the source or n+ n+
drain diffusion regions
p-type body
embedded in the substrate. b
The source-substrate and
drain-substrate junctions are
reverse biased under normal
operating conditions.
The amount of junction
capacitance is a function of
applied terminal voltages
 Junction Capacitances
All junctions are assumed to
be abrupt.
Given that the depletion
2 Si N A N D
thickness is xd we can
compute the depletion
xd 0 V
q N AND
capacitance of a reverse
biased abrupt pn-junction.

Where NA and ND are the n-

type and p-type doping
densities respectively, V is the
negative reverse bias voltage.
kT N A N D
0 ln

The built-in junction potential q ni2
is:
 Junction Capacitances
The junction is forward biased for
a positive voltage V and reverse
biased for a negative voltage V.
The depletion region charge
stored in this area in terms of xd is N N N N
Q j Aq A D xd A 2 Si q A D 0 V
N A ND N A ND
A stands for the junction area.
The junction capacitance
associated with the depletion
region is defined as:
dQ j
Cj
dV

If we differentiate the equation

describing Qj with respect to the
bias voltage we get Cj.
 Junction Capacitances
We can write the junction
capacitance Si q N A N D
C j V A
1



2 N A N D 0 V
If the zero bias capacitance is:
Si q N A N D 1
in a more general form as C j0
2 N A N D 0

m is the gradient coefficient C j (V )

AC j 0
and is 0.5 for abrupt junctions V
m

and 1/3 for linearly graded 1

junction profiles 0
The value of the junction
capacitance ultimately
depends on the external bias
voltage applied across the pn-
junction.
 Junction Capacitances
The sidewalls of a typical
MOSFET source or drain
diffusion region are surrounded
by a p+ channel stop implant
having a higher doping density
than the substrate doping density
NA.
The sidewall zero bias
capacitance is Cj0sw and will be
different from the previously
discussed junction capacitance.
The zero-bias capacitance per unit
area can be found as follows:
Si q N A( sw) N D 1
C j 0 sw
2 N A( sw) N D 0( sw)
Where NA(sw) is the sidewall
doping density, 0(sw) is the built-
in potential of the sidewall
junctions.
All sidewalls in a typical diffusion
structure have approximately the
same junction depth xj.
The zero bias sidewall junction
capacitance per unit length is:
C jsw C j 0 sw x j
 MOS Capcitances
Beyond the steady state behavior
of the MOS transistor.
In order to examine the transient
(AC) response of MOSFETs the
digital circuits consisting of
MOSFETs we have to determine
the nature and amount of parasitic
capacitances associated with the
MOS transistor.
On chip capacitances found on
MOS circuits are in general
complicated functions of the
layout geometries and the
manufacturing processes.
Most of these capacitances are not
lumped but distributed and their
exact calculations would usually
require complex three
dimensional nonlinear charge-
voltage models.
A lumped representation of the
capacitance can be used to
analyze the dynamic transient
behavior of the device.
The capacitances can be classified
as oxide related or junction
capacitances and we will start the
analysis with the oxide related
capacitances.
 MOS Capacitances
Cgb D
Cgd
Cdb
These are Cgs and Cgd
G B
respectively.
Csb
If both the source and drain
Cgs
regions have the same width (W),
S the overlap capacitance becomes:
Cgs=CoxWLD and Cgd=CoxWLD.
Masks result in some These overlap capacitances are
regions having overlaps, voltage dependent.
for example the gate Cgs, Cgd and Cgb are voltage
electrode overlaps both the dependent and distributed
source and drain regions at They result from the interaction
the edges. between the gate voltage and the
Two overlap capacitances channel charge.
arise as a result.
MOS Capacitance Model
Simply viewed as parallel plate
capacitor
Gate-Oxide-Channel
C = Cg = oxWL/tox = CoxWL
Define
Cpermicron = CoxL = oxL/tox
 MOS Oxide Capacitances
The gate-to-source capacitance is
actually the gate-to-channel
capacitance seen between the gate
and the source terminals.
The gate-to-drain capacitance is
actually the gate-to-channel
capacitance seen between the gate
and the drain terminals.
In Cut-off mode the surface is not
inverted and there is no
conducting channel linking the
surface to the source and to the
drain.
The gate-to-source and gate-to-
drain capacitances are both equal
to zero (Cgs=Cgd=0).
The gate-to-substrate capacitance
can be approximated by:
Cgb=CoxWL
In linear mode the inverted
channel extends across the
MOSFET between the source and
drain. This conducting inversion
layer on the surface effectively
shields the substrate from the gate
electric field making it Cgb=0.
 MOSFET Oxide Capacitance
In linear mode the distributed The source is however still linked
gate-to-channel capacitance to the conducting channel. It
maybe viewed as being shared shields the gate from the channel
equally between the source and leading to Cgb of zero.
the drain leading to: The distributed gate-to-channel
Cgs=Cgd=0.5CoxWL capacitance as seen between the
If the MOSFET is operating in gate and the source is
saturation mode the inversion approximated by: Cgs2/3CoxWL.
layer on the surface does not
extend to the drain, but is pinched
off.
The gate-to-drain capacitance in
therefore zero (Cgd=0).
 MOS Gate Capacitances
Cap Cutoff Linear Saturation

Cgb C0 0 0

Cgs 0 C0/2 2/3C0

Cgd 0 C0/2 0

Cg=Cgs+Cgd+Cgb C0 C0 2/3C0
 Velocity Saturation
Ideal carrier velocity relation:
v = mE
E = Vds/L
In reality velocity does not increase forever
with applied field
For high values of Applied field, E ~
10000V/cm
v= mE/(1+E/Esat)
Velocity Saturation and Mobility
Degradation
Recall ideal current equation

I ds Vgs Vt dsat V
V
dsat
2

Vgs Vt
2

2

With velocity saturated at v=vsat

I ds C oxW (V gs Vt )v sat
 Velocity Saturated Current
Modeling
Cutoff
Ids = 0: Vgs<Vt

Linear I dsat Pc (V gs Vt )
Ids = IdsatVds/Vdsat:
2
Vds<Vdsat
Saturation Vdsat Pv (Vgs Vt ) / 2
Ids = Idsat: Vds>Vdsat
Modeling with empirical
parameters
between 2(ideal) to
1(compeletely velocity
saturated
 Velocity Saturation

The critical E-field at which

scattering effects occur depends on
the doping levels and the vertical
electric field applied.
Velocity saturation effects are less
pronounced in pMOS devices.
By increasing VDS the electrical field
in the channel ultimately reaches the
critical value and the carriers at the
drain become velocity saturated.
Further increasing VDS does not result
in increased ID. The current saturates
at IDSAT
The behavior of the MOS transistor is
better understood by analysis of the I-
V curves.