Introduction

The GreenDroid mobile application processor is a 45-nm multicore

research prototype that targets the Android mobile-phone software
stack.

It can execute general-purpose mobile programs with 11 times less

energy than todays most energy-efficient designs, at similar or better
performance levels.
 Working
It does this through the use of a
hundred or so automatically
generated, highly specialized, energy-
reducing cores, called conservation
cores.
Major technological
problem for
Microprocessor Architects
 Necessity
A key technological problem for microprocessor architects is the
utilization wall.
The utilization wall says that, with each process generation, the
percentage of transistors that a chip design can switch at full
frequency drops exponentially because of power constraints.

A direct consequence of this is Dark Silicon

Dark Siliconlarge swaths of a chips silicon area that must remain

mostly passive to stay within the chips power budget.
 Currently, only about 1 percent
of a modest-sized 32-nm mobile
chip can switch at full frequency
within a 3-W power budget.

With each process generation,

dark silicon gets exponentially
cheaper, whereas the power
budget is becoming
exponentially more valuable.
 What is Power Budget ??
A power budget shows where all the possible power will be used by a
device to by breaking it down into components and categories.

In some situations, you might be told up front that you will have 3W
available to run your design.

However, sometimes as designers start by calculating the total power

a system needs and then taking actions such as replacing parts or
redesigning circuits to cut back power to an acceptable level.
 The Utilization Wall
Scaling theory Classical scaling
Transistor and power budgets no longer balanced Device count S2
Exponentially increasing problem! Device frequency S
Device power (cap) 1/S
Expected utilization for fixed area
and power budget Device power (Vdd) 1/S2
1.0

0.9
Utilization 1
0.8 Leakage limited scaling
0.7
Device count S2
0.6

0.5
Device frequency S
0.4 Device power (cap) 1/S
0.3 Device power (Vdd) ~1
0.2
Utilization 1/S2
0.1

0.0
90nm 65nm 45nm 32nm
 The Utilization Wall
2
Utilization @ 300mm & 80w
Experimental results
0.20
Replicated small data path 17.6%
0.18
More Dark Silicon than active
0.16
0.14
0.12
Observations in the wild 0.10
Flat frequency curve
0.08
Turbo Mode 6.5%
0.06
Increasing cache/processor ratio 3.3%
0.04
0.02
0.00
90nm 45nm 32nm
TSMC TSMC ITRS
Utilization Wall: Dark Implications for Multicore

.
Spectrum of tradeoffs
between # cores and
frequency.
2x4 cores @ 3 GHz
e.g.; take (8 cores dark)
65 nm32 nm; (Industrys Choice)
i.e. (s =2)

.
4 cores @ 3 GHz
.

4 cores @ 2x3 GHz

(12 cores dark)

65 nm 32 nm
 Key Insights
The research leverages two key insights:

First, it makes sense to find architectural techniques that trade this

cheap resource, dark silicon, for the more valuable resource, energy
efficiency.

Second, specialized logic can attain 10X to 1,000X better energy

efficiency over general-purpose processors.
 Approach
Dark Silicon
The approach is to fill a chips dark silicon area with
specialized cores to save energy on common
applications.

These cores are automatically generated from the code

base that the processor is intended to runthat is, the
Android mobile-phone software stack.

The cores feature a focused re-configurability so that

they can remain useful even as the code they target
evolves.
 The GreenDroid architecture
The GreenDroid architecture uses specialized, energy-efficient
processors, called conservation cores, or c-cores to execute
frequently used portions of the application code.

Collectively, the c-cores span approximately 95 percent of the

execution time of teams test Android-based workload.
The high-level architecture of a GreenDroid system
The system comprises an
array of 16 non-identical
tiles.
Each tile holds components
common to every tilethe
CPU, on-chip network (OCN),
and shared Level 1 (L1) data
cacheand provides space
for multiple conservation
cores (c-cores) of various sizes
The c-cores are tightly coupled
to the host CPU via the L1 data
cache and a specialized
interface
 Conservation Cores
Hot code
Specialized cores for reducing energy
Automatically generated from hot
regions of program source C-Core
D cache
Patching support future proofs HW

Fully automated toolchain

Drop-in replacements for code
Hot code implemented by C-Core, cold Host I cache
code runs on host CPU
CPU
HW generation/SW integration (general purpose)

Energy efficient
Up to 16x for targeted hot code
Cold code
Figure shows the projected energy
savings in GreenDroid and the origin
of these savings.
The savings come from two sources
First, c-cores dont require
instruction fetch, instruction decode,
a conventional register file, or any of
the associated structures. Removing
these reduces energy consumption
by 56 percent.
The second source of savings (35 %
of energy) comes from the
specialization of the c-cores data
path.
The result is that average per-
instruction energy drops from 91 pJ
per instruction to just 8 pJ per
instruction.
 Marching Toward Completion
The toolchain automatically generates placed-and-routed c-core
tiles, given the source code and information about execution
properties.
The cycle- and energy-accurate simulation tools have confirmed the
energy savings provided by c-cores.
The team is currently working on more detailed full-system Android
emulation to improve our workload modeling so that they can finalize
the selection of c-cores that will populate GreenDroids dark silicon.
In parallel with this effort, they are working ontiming closure and
physical design.
 The Research Team
The University of California,San Diego,USA. Massachusetts Institute of
Technology (MIT),USA
Assistant professors PhD students Postdoctoral Researcher
Michael Bedford Taylor Nathan Goulding-Hotta Jonathan Babb
Ganesh Venkatesh
Steven Swanson
Saturnino Garcia
Postdoctoral scholar Manish Arora
Jack Sampson Siddhartha Nath
Graduate Students
Vikram Bhatt
Joe Auricchio
Po-Chao Huang
 Conclusions
Over the next five to 10 years, the breakdown of conventional silicon
scaling and the resulting utilization wall will exponentially increase
the amount of dark silicon in both desktop and mobile processors.
The GreenDroid prototype demonstrates that c-cores offer a new
technique to convert dark silicon into energy savings and increased
parallel execution under strict power budgets.
The estimate that the prototype will reduce processor energy
consumption by 91 percent for the code that c-cores target, and
result in an overall savings of 7.4 X.

22
 Reference
Based on April 2011 IEEE Micro paper.

THE GREENDROID MOBILE APPLICATION PROCESSOR:

AN ARCHITECTURE FOR SILICONS
DARK FUTURE
http://greendroid.ucsd.edu/