DESIGN OF RTL MODEL AND VERIFICATION

FOR HYPERFLASH S26KS512S

Students Instructors

12PFIEV2 Trn Nguyn Yn Nhi Dr.L Quc Huy

Industrial information Trn Th Ngc Trm En.H Hu Hin

 Content

Overview of IC design

Softmodel development & Verification Flow

Design Object: HyperFlash S26KS512S

RTL Design

Writing testcases for verifying the functions of

the design
 1. Overview of IC design

Currently, the IC design industry has

become the spearhead industry of many
countries in the world. In Vietnam, it is a
new field that is tending to develop.
In IC design, the Register Transfer Level
(RTL) is a critical starting point that greatly
influences subsequent steps in the design
flow.
It also needs to be tested to ensure that the
design is no error and performs the required
function properly.
UVM (Universal Verification Methodology) is
the complete and best method for efficient
and comprehensive testing, with the
support of the System Verilog code library.
 The common object to design is flash
memory
The demand for data storage on handheld
devices is rising. As semiconductor
technology was born and developed,
allowing for increased storage density,
memory flash was replaced by a dedicated
controller to manage read and write
operations.
Prior to the widespread adoption and
development of Flash memory, we chose
the RTL model design and verification
Hyperfash memory S26KS512S.
 2. Softmodel development & Verification Flow

Specification

Define test scenario in detail .

RTL coding Softmodel generation Test plan Define covergroups/coverpoints/bins

UVM testbench Uvm environment,sequences,

development testcases coding

Run simulation foreach testcases

Checking for syntax Function Simulation +
and synthesizable Lint check Debug & update rtl/uvm environment
Debug if its operation mismatch with specs

Run regression + get Run all testcases multiple times

to collect functional / code
coverage report Coverage.

Veloce synthesis Generate gate-level netlist

mapped into Emulator

Veloce Emulator Veloce runtime and debug

 3. Design Object HyperFlash S26KS512S

Signal Descriptions
Symbol Descriptions
CS# Chip select, transactions are initiated with CS#
HighLow, terminated with Low High
CK, CK# Differential Clock
RWDS Read Write Data Strobe, Output data during read
transactions are edge aligned with RWDS.
DQ[7:0] Data Input / Output. Command / Address / Data
information is transferred on these DQs during read
and write transactions
INT# Interrupt output
RESET# Hardware Reset. When Low, the device will self
initiaize and return to the array read state. RWDS and
DQ[7:0] are placed into the High-Z state when RESET#
is Low
RSTO# Reset output
Vcc Core power
VccQ Input/ Output power
Vss Core ground
VssQ Input/ Output ground
 Read Operation
A read access requires two clock cycles to define the target half-page
address [CA37:CA16] and the burst type (linear burst hay wrapped burst).
The host then continues clocking for a number of Initial Latency cycles that
are installed in the Configuration Register
During the initial latency period the third clock cycle will specify the starting
address
Once these latency clocks have been completed the memory starts to
simultaneously transition the Read Write Data Strobe (RWDS) and begins
outputting the target data

7
 Hot ng ghi
Write Operations
A write operation starts with the first three clock cycles providing the
CAx (Command / Address) information indicating the transaction
characteristics
Immediately following the CA information the host is able to transfer the
write data on the DQ bus
RWDS will be driven Low as long as CS# is Low

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 Program methods

Word Programming
Word programming is used to
program a single word or multi
word (maximum of 256 words)
The Word Programming command
sequence:
Address 555h, Data AAh: unlock
command 1
Address 2AAh, Data 55h: unlock
command 2
Address 555h, Data A0h: set up
command
Address : Program address, Data:
Program data

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 Write Buffer Programming
Write Buffer Programming
Write Buffer Programming allows up to 512 bytes to be programmed in one
operation
Sequence Address Data Comment
Issue Unlock Command 1 555 AA
Issue Unlock Command 2 2AA 55
Issue Write to Buffer Command SA 0025h
at Sector Address
Issue Number of Locations at SA WC WC = number of words to program minus 1
Sector Address
Example:
WC of 0 = 1 word to program
WC of 1 = 2 words to program
Load Starting Address/Data pair Staring PD Selects a Line and loads first Address/Data pair
address
Load next Address/Data pair WB PD All address must be within the select Line
boundaries and have to be loaded in sequential
Location
order
Load last Address/Data WB PD All address must be within the select Line
boundaries and have to be loaded in sequential
Location
order
Issue Write Buffer Program SA 0029h This command must follow the last write buffer
Confirm at Sector Address location loaded, or operation will Abort 10
 Write Buffer Programming
Sequence will be Aborted
under the following conditions:
Load a Word Count value
greater than 255.
Write an address that is outside
the Line provided in the Write
to Buffer command.
The Program Buffer to Flash
command is not issued after
the Write Word Count number
of data words is loaded

The Write Buffer Abort error

status can be cleared by
writing:
Write Buffer Abort Reset
command
Status Register Clear
command

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 Erase Methods
Chip Erase
The Chip Erase function erases the entire Flash Memory Array. After a
successful Chip Erase, all locations within the device contain FFFFh.
The Chip Erase command sequence
Sequence Address Data
Unlock Command 1 555h AAh
Unlock Command 2 2AAh 55h
Set up Command 555h 80h
Unlock Write Command 1 555h AAh
Unlock Write Command 2 2AAh 55h
Chip Erase Command 555h 10h

The system can determine the status of the erase operation by reading the
Status Register

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 Sector Erase
The Sector Erase function erases one sector in the memory array. After a
successful sector erase, all location within the erased sector contain FFFFh.

The Sector Erase command sequence

Sequence
Sequence Address Data
Unlock Command 1 Address555h AAh
Unlock Command 2 2AAh 55h
Data
Set up Command 555h 80h
Unlock Write Command 1 555h AAh
Unlock Write Command 2 2AAh 55h
Sector Erase Command Sector Address 30h

The system can determine the status of the erase operation by reading the
Status Register

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 Chng 4: Thit
4. RTL k RTL
Design
Funtional Block Diagram

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 Finite State Machine Diagram

READ

Wr && unlock 1

READUL1 Wr

Wr && unlock 2
Wr && CM_WB Wr && CM_LVCR Load
A WB READUL2
VCR
Wr && CM_PG Wr && CM_RVCR
Wr && CM_ER
Read Wr
ER
VCR
PG1
Wr && unlock 1

Wr
ERUL1

B Wr && unlock 2
PG

P_done ERUL2
Wr && CM_SER Wr && CM_CER

SER CER

E_done E_done
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 Finite State Machine Diagram

Sec_addr !=sa_pgm && WC>256

A WB

Sec_addr==sa_pgm && WC<256

Sec_addr==sa_pgm && cnt=0 WB load Sec_addr !=sa_pgm

first word

PGE
Sec_addr==sa_pgm && cnt>0

Sec_addr !=sa_pgm
WB load w_line !=wb_line Wr && unlock 1
next word

Sec_addr==sa_pgm &&
w_line==wb_line && cnt>0 PGEUL1 CM_SR_CLR
Sec_addr !=sa_pgm,
WB not CM_WB_ CF Wr && unlock 2
confirm
PGEUL2

Sec_addr==sa_pgm && CM_WB_ CF

CM_RST

READ
B PG
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5.Writing testcases for verifying the function of the designed
HyperFlash Memory S26ks512s

Testplan
Testplan is an excutable document listing different scenarios to
demonstrate that the DUT will work according to specification
requirements and will not have any unexpected situations.
It is achieved by using the excel tool to fully enumerate the
scenarios that are executed, instructions for performing the test
process.
The Testplan is divided into 3 items: read operation, write operation,
and erase operation.
Each activity is divided into one or more covergroup. The
covergroup structure encapsulates the specification of a coverage
model.
 Chng 2: Kim tra thit k bng cng c UVM

Setup testbench
 Chng 5: Vit testcase kim tra chc nng thit k
FlashMemory S26KS512
Write testcase code
Based on the testplan, write testcases using the system verilog
language that checks for the three functions of the hyperflash: read,
write, and erase
Verify reading function
Through its characteristic features, burst type, clock latency, burst
lenghth.
Include testcases:
1. read_while_program_word.oo.sv
2. read_with_latency16.oo.sv
3. read_wrapped_burst_write_buffer.oo.sv
 Simulation
Loaded by word programming
Addr: 170000h
Data :bd3b 35b8 6474 61b2 ..
Addr: 170000h
Data :bd3b 35 b8 6474 61b2 ..
All data read out is the same as the data loaded

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 Chng 5: Vit testcase kim tra chc nng thit k
FlashMemory S26KS512

Verify writting function

The programming operation will be tested by the number of word
count, page or half-page count, performed with the sector and
program under normal or busy conditions, followed by two types of
word programing and write_buffer programming
Include testcases :
1. busy_program_one_word.oo.sv
2. normal_program_one_word.oo.sv
3. busy_program_multi_word.oo.sv
4. normal_program_multi_word.oo.sv
 Chng 5: Vit testcase kim tra chc nng thit k
FlashMemory S26KS512
Write buffer programming
Include testcases:
1. normal_write_buffer_SA255.oo.sv
2. busy_write_buffer_SA255.oo.sv
3. normal_write_buffer_one_page.oo.sv
4. busy_write_buffer_one_page.oo.sv
5. normal_write_buffer_one_word.oo.sv
6. busy_write_buffer_one_word.oo.sv
7. normal_write_buffer_256_word.oo.sv
8. busy_write_buffer_256_word.oo.sv
9. normal_write_buffer_full_sector.oo.sv
10. busy_write_buffer_full_sector.oo.sv
11. write_buffer_abort_status_clear_r.oo.sv
12. write_buffer_abort_reset.oo.sv
Simulation
Load data by write buffer programming with 256 word
Addr 1d40000h 1d40001h

Data 1e8ch 8482h .

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Last addr = 1d400ff, data: d1bb
After Loading 256 words execute the confirm command with addr=
1d40000h

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 Chng 5: Vit testcase kim tra chc nng thit k
FlashMemory S26KS512

Verify erasing function

Sector erase
Verify the erase function under normal or busy conditions through
sector characteristics under the following testcases:
1. normal_sector0_erase.oo.sv
2. busy_sector0_erase.oo.sv
3. normal_sector255_erase.oo.sv
4. busy_sector255_erase.oo.sv
5. normal_random_sector_erase.oo.sv
6. busy_random_sector_erase.oo.sv
Chip erase
normal_chip_erase.oo.sv
 Simulation
Load data by word program with multiple words
Addr=1ffff00h
Data=c1ef 00f8 55c1 4748 844f

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After sector erase command is complete , Reread the data and see
all positions in erased sector contains FFFFh

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 Chng 5: Vit testcase kim tra chc nng thit k
FlashMemory S26KS512
o Simulation
Compile any test file to check whether any error occurred with the
following command:
prj_setup.py --tst_name=
<testcase_name>usr_def_comp="+define+PURE_OO
+define+SPEEDSIM " --timescale=1ps/1ps --dump_vpd
At the end of each simulation, a TEST FAILED or TEST PASSED
report will be generated. Log files and Waveform viewers can help
debug further if the test fails.
View waveform with following command:
show_wf.sh scratch/s26ks512s/sim/<testcase_name>_RTL/
<testcase_name>.vpd views/s1.vpd.tcl &
Each waveform for each testcase will produce the same sequence
as the scenario given in the testplan
 Chng 5: Vit testcase kim tra chc nng thit k
FlashMemory S26KS512
Evaluation criteria
Code coverage will be
a measure of the
performance of the
RTL performed by the
simulator while
running testcases
The evaluation criteria
used to test whether
the testbench has met
design requirements
Measure the
effectiveness of
performance verifying
design functions
Code coverage scoreboard
 Chng 5: Vit testcase kim tra chc nng thit k
FlashMemory S26KS512
Comment :
Through the wave sequence shown on the waveform, the RTL
design is almost true for read, write and erase functions as required
by the spec.
The percentage of code coverage shows almost complete
inspection:
1. Coverage on each line of code
2. Coverage by block
3. Coverage under conditions, operations
4. Coverage by branch
5. Coverage according to the up, down (logical level 0/1) of the signal
6. Coverage of the finite state machine
 Chng 5: Vit testcase kim tra chc nng thit k
Conclusions
FlashMemory S26KS512

Through the research and implementation of the topic we have

accumulated many useful knowledge :
Get familiar with the Linux environment to ensure the security of
data
Get the basics of verilog hardware description language.
Understand the use of UVM verification methods
Understand the HyperBus protocol and the processes of read, write,
erase of Flash Memory.
Make rtl design for HyperFlash S26ks512s matching requirements
of spec
Perform the relative completeness of cases to verify
 Chng 5: Vit testcaseand
Limitations kim tra chc nngdirection
development thit k
FlashMemory S26KS512

Due to time constraints, we have only excute some basic functions

of HyperLash S26KS512S.
Only use code coverage to check the number of code verified but
not functional coverage to evaluate the coverage of the design
based on the feature being verified .
Only simulated to check the waveform on the software but not
synthesis generated netlist and actual implementation should still
have many restrictions.
In the coming time after graduation, we will continue to improve our
topic.