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C= A AND B
architecture Behavioral of ha is
begin
s <= a xor b ;
c <= a and b ;
end Behavioral
Full Adder
The difference between a half-adder and a full-adder is that the full-adder
has three inputs and two outputs,
whereas half adder has only two inputs and two outputs.
The first two inputs are A and B and the third input is an input carry as C-
IN.
When a full-adder logic is designed, you string eight of them together to
create a byte-wide adder and cascade the carry bit from one adder to the
next.
Purpose of Including Carry In and Carry Out Flags
When adding numbers using circuits it is necessary to look at each
bit of a number at a time.
The least significant bits are added first, with a carry in flag set to 0.
The next two least significant bits are added together, using a carry
in flag set to the carry out flag of the previous operationg.
S2
S3
entity fu is
Port (a,cin: in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end fu;
architecture Behavioral of fu is
signal S1, S2, S3 : std_logic;
begin
S1 <= a xor b ;
s <= S1 xor cin;
S2 <= S1 and cin;
S3 <= a and b;
c<= S2 or S3;
end Behavioral;
MULTIPLEXER
In electronics, a multiplexer or mux is a device that selects
one of several analog or digital input signals and forwards
the selected input into a single line.
At any given time, one and only one device is using the line.
INPUT OUTPUT
S1 S2 Q
0 0 A
0 1 B
1 0 C
1 1 D
CODE
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_4to1 is
port( A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_4to1;
architecture bhv of mux_4to1 is
begin
process (A,B,C,D,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
Z <= A;
elsif (S0 ='1' and S1 = '0') then
Z <= B;
elsif (S0 ='0' and S1 = '1') then
Z <= C;
else
Z <= D;
end if;
end process;
end bhv;
TestBench Code for 4 to 1 Multiplexer
A <= '1';
B <= '0';
C <= '1';
D <= '0';
S0 <= '0'; S1 <= '0';
wait for 100 ns;
S0 <= '1'; S1 <= '0';
wait for 100 ns;
S0 <= '0'; S1 <= '1';
wait for 100 ns;
S0 <= '1'; S1 <= '1';
wait;
Control
4
A
4
4- Bit ALU RESULT
4
B
A
B
INPUT C Q OUTPUT
S1 S2
4 : 1 Mux