INTRODUCTION TO

EMBEDDED SYSTEMS
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BUS STRUCTURE

Created by Mr. THOMAS KWANTWI 11/24/2017

 BUS
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Bus is the mechanism by which the CPU

communicates with memory and I/O devices
Bus is not just a collection of wires
Bus defines the protocol for communication

Created by Mr. THOMAS KWANTWI 11/24/2017

 Bus
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Shared communication link

Single set of wires used to connect multiple
subsystems
A bus is also a fundamental tool for composing
large, complex systems

Created by Mr. THOMAS KWANTWI 11/24/2017

 What defines a bus?
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Transaction Protocol

Timing and Signaling Specification

Bunch of Wires

Electrical Specification

Physical/Mechanical Characteristics- the

connectors
Created by Mr. THOMAS KWANTWI 11/24/2017
 Generic bus structure
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Address
Data
Control

Created by Mr. THOMAS KWANTWI 11/24/2017

 Generic Organization of a Bus
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Control lines:
Signal requests and acknowledgements
Indicate what type of information is on the data lines
Data lines carry information between the source and
the destination:
Data and Addresses
Address: special form of data
Complex commands

Created by Mr. THOMAS KWANTWI 11/24/2017

 Bus Characteristics
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Bus signals are usually tri-stated

Address and data lines may be multiplexed
Every device on the bus must be able to drive the
maximum bus load:
Bus wires
Other bus drives
Bus may include clock signal
Timing is relative to clock

Created by Mr. THOMAS KWANTWI 11/24/2017

 Increasing the Bus Bandwidth
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Non-multiplexed address and data lines:

Address and data can be transmitted in one bus cycle if separate
address and data lines are available
Cost (a) more bus lines, (b) increased complexity
Data bus width:
By increasing the width of the bus, transfers of multiple words
require fewer bus cycles
Cost: more bus lines
Block transfers:
Allow the bus to transfer multiple words in block-to-block bus cycles
Only one address needs to be sent at the beginning
The bus is not released until the last word is transferred
Cost: (a) increased complexity
(b) decreased response time for request

Created by Mr. THOMAS KWANTWI 11/24/2017

 Advantages of Bus
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Versatility:
New devices can be added easily
Low cost:
A single set of wires is shared in multiple ways

Created by Mr. THOMAS KWANTWI 11/24/2017

 Disadvantages of Bus
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It creates a communication bottleneck

The bandwidth of the bus can limit the maximum I/O
throughput
The maximum bus speed is largely limited by:
The length of the bus

The number of devices on the bus

The need to support a range of devices with:

o Widely varying latencies

o Widely varying data transfer rates

Created by Mr. THOMAS KWANTWI 11/24/2017

 Parallel communication
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Multiple data, control, and possibly power wires

One bit per wire

High data throughput with short distances

Typically used when connecting devices on same IC
or same circuit board
Bus must be kept short
o Long parallel wires result in high capacitance values which
require more time to charge/discharge
o Data misalignment between wires increases as length increase
Higher cost, bulky

Created by Mr. THOMAS KWANTWI 11/24/2017

 Serial communication
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Single data wire, possible also control and power

wires
Words transmitted one bit at a time
Higher data throughput with long distances
Less average capacitance, so more bits per unit of time
Cheaper, less bulky
More complex interfacing logic and communication
protocol
Sender needs to decompose word into bits
Receiver needs to recompose bits into word
Control signals often sent on same wire as data increasing
protocol complexity
Created by Mr. THOMAS KWANTWI 11/24/2017
 Synchronous Bus
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Includes a clock in the control lines

A fixed protocol for communication that is relative to
the clock
Advantages: involves very little logic and can run
very fast
Disadvantages:
Every device on the bus must run at the same clock rate
To avoid clock skew, they cannot be long if they are fast
Most processor-memory buses

Created by Mr. THOMAS KWANTWI 11/24/2017

 Asynchronous Bus
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Asynchronous Bus:
It is not clocked

It can accommodate a wide range of devices

It can be lengthened without worrying about clock skew

It requires a handshaking protocol

Created by Mr. THOMAS KWANTWI 11/24/2017

 Basic Protocol Concepts
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A bus transaction includes two parts:

Issuing the command (and address)- request

Transferring the data action

Master is the one who starts the bus transaction by:

Issuing the command (and address)

Slave is the one who responds to the address by:

Sending data to the master if the master ask for data

Receiving data from the master if the master wants to send

data

Created by Mr. THOMAS KWANTWI 11/24/2017

 Bus Arbitration
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One of the most important issues in bus design:

How is the bus reserved by a device that wishes to use it?

Master slave arrangement:

Only the bus master can control access to the bus:
it initiates and controls all bus requests
A slave responds to read and write requests
The simplest system:
Processor is the only bus master

All bus requests must be controlled by the processor

Major drawback: the processor is involved in every transaction

Created by Mr. THOMAS KWANTWI 11/24/2017

 Bus Transaction protocols
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Strobe Protocol
Master asserts REQ to receive data
Slave puts data on bus within time frame T(access)
Master receives data and de-asserts REQ
Slave becomes ready for next REQ

Handshake Protocol
Master asserts REQ to receive data
Slave puts data on bus and sends an assert ACK
Master receives data and de-assert REQ
Slave becomes ready for next REQ

Strobe/Handshake combination
Master asserts REQ to receive data
Slave cant put data within T(access) so it asserts WAIT
Slave puts data on bus and de-asserts WAIT
Master receives data and de-asserts REQ
Slave becomes ready for next REQ

Created by Mr. THOMAS KWANTWI 11/24/2017

 Bus Transaction protocols
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When to use Handshake?

When response time cannot be guaranteed in advance:
Data-dependent delay
Component variations

Created by Mr. THOMAS KWANTWI 11/24/2017

 Bus Transaction protocols
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ISA bus protocol memory access

ISA: Industry Standard Architecture

Features
20-bit address
Compromise strobe/handshake control
4 cycles default
Unless CHRDY de-asserted resulting in additional wait
cycles(up to 6)

Created by Mr. THOMAS KWANTWI 11/24/2017

 Arbitration for Multiple Potential Bus Masters
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Bus arbitration schemes usually try to balance two

factors:
Bus priority: the highest priority device should be serviced first
Fairness: Even the lowest priority device should never be
completely locked out from the bus
Bus arbitration schemes can be divided into four broad
classes:
Daisy chain arbitration
Centralized, parallel arbitration
Distributed arbitration by self-selection: each device wanting the bus
places a code indicating its identity on the bus
Distributed arbitration by collision detection: each device just go for
it.

Created by Mr. THOMAS KWANTWI 11/24/2017

 The Daisy Chain Bus Arbitration
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Advantage: Simple
Disadvantage:
Cannot assure fairness: a low-priority device may be locked
out indefinitely
The use of the daisy chain grant signal also limits the bus
speed

Created by Mr. THOMAS KWANTWI 11/24/2017

 Centralized Parallel Arbitration
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Used in essentially all processor-memory busses and

in high-speed I/O busses

Created by Mr. THOMAS KWANTWI 11/24/2017

 Arbitration: Priority arbiter
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Types of priority
Fixed priority
Each peripheral has unique rank
Highest rank chosen first with simultaneous requests
Preferred when clear difference in rank between peripherals

Rotating priority (round-robin)

Priority changed based on history of servicing
Better distribution of servicing especially among peripherals with
similar priority demands.

Created by Mr. THOMAS KWANTWI 11/24/2017

 Arbitration using a priority arbiter
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Created by Mr. THOMAS KWANTWI 11/24/2017

 Arbitration using a priority arbiter
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Steps involved
Microprocessor is executing its program
Peripheral 1 and Peripheral 2 needs servicing so asserts IREQ1 and
IREQ2
Priority arbiter sees at least one IREQ input asserted, so asserts INT
Microprocessor stops executing its program and stores its state.
Microprocessor asserts INTA
Priority arbiter asserts IACK1 to acknowledge peripheral 1.
Peripheral 1 puts its interrupt address vector on he system bus
Microprocessor jumps to the address of ISR read from data bus, ISR
executes and returns.
Microprocessor resumes executing its program.

Created by Mr. THOMAS KWANTWI 11/24/2017

 Increasing Transaction Rate on Multi-master Bus
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Overlapped arbitration
Perform arbitration for next transaction during current transaction
Bus parking
Master holds onto bus and performs multiple transactions as long as
no other master makes request
Overlapped address/ data phases
Requires one of the above techniques
Split-phase (or packet switched) bus
Completely separate address and data phases
Arbitrate separately for each
Address phase yield a tag which is matched with data phase

Created by Mr. THOMAS KWANTWI 11/24/2017

 Direct Memory Access(DMA)
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Direct transfer of data by-passing CPU

Using DMA controller
Separate single-purpose processor

Microprocessor relinquishes control of system bus to DMA

controller
Microprocessor can meanwhile execute its regular program
o No inefficient storing and restoring state due to ISR call
o Regular program need not wait unless it requires the system bus
o Harvard architecture processor can fetch and execute
instructions as long as they dont access data memory if they do,
processor stalls

Created by Mr. THOMAS KWANTWI 11/24/2017

 Direct Memory Access(DMA)
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Peripheral to Memory transfer with DMA

Created by Mr. THOMAS KWANTWI 11/24/2017

 Multilevel Bus Architectures
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One bus for all communication

Peripherals would need high-speed, processor-specific bus
interface
Excess gates, power consumption, and cost: less portable
Too many peripherals slow down bus

Created by Mr. THOMAS KWANTWI 11/24/2017

 Multi-level Buses
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Processor-local bus
High speed, wide, most frequent communication

Connects microprocessor, cache, memory controllers, etc.

Peripheral bus
Lower speed, narrower, less frequent communication

Typically industry standard (ISA, PCI)for portability

Bridge
Single-purpose processor converts communication between
busses

Created by Mr. THOMAS KWANTWI 11/24/2017

 Parallel Protocol: PCI Bus
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PCI Bus (Peripheral Component Interconnect)

High performance bus originated at Intel in the early 1990s

Standard adopted by industry and administered by PCISIG

(PCI Special Interest Group)
Interconnects chips, expansion boards, processor memory
subsystems
Data transfer rates of 127.2 to 508.6 Mbit/s and 32-bit
addressing
Synchronous bus architecture

Multiplexed data/address lines

Created by Mr. THOMAS KWANTWI 11/24/2017

 PCI Bus Architecture
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Created by Mr. THOMAS KWANTWI 11/24/2017

 PCI Read/Write Transactions
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All signals sampled on rising edge

Centralized Parallel Arbitration
Overlapped with previous transaction
All transfer are burst
Address phase starts by asserting FRAMME
Next cycle initiator asserts cmd and address
Data transfer happen on when
IRDY is asserted by target when ready to transfer data
TRDY asserted by target when ready to transfer data
Transfer when both asserted on the rising edge
FRAME de-asserted when master intends to complete
only one more data transfer

Created by Mr. THOMAS KWANTWI 11/24/2017

 PCI Variants for Embedded Systems
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PC/104: Embedded system version of the ISA bus

Incorporate 16 and x86 processors running at 16 to 33 Mhz

Bandwidth: 5 Mbytes/s

PC/104: Standard that specifies size card with both

ISA and PCI
Enabling use of Pentium CPU in Embedded system
A new form factor and a pass through connector

Created by Mr. THOMAS KWANTWI 11/24/2017