Analog and Digital VLSI Design

EEE F313/INSTR F313

Lecture 22: Techniques for delay minimization,

dynamic logic
 First order Analysis
Simple Transistor sizing in gates

Progressive Transistor sizing in gates

Input Reordering

Logic Restructuring
 Considering Capacitances

A B C D

A CL
B C3
C C2
D C1
Distributed RC model
(Elmore delay)

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

 Technique 1 : Progressive Sizing
Transistor sizing
as long as fan-out capacitance dominates

Progressive sizing
Distributed RC line
InN MN CL M1 > M2 > M3 > > MN

(the mosfet closest to the output

In3 M3 C3 should be the smallest)
In2 M2 C2
In1 M1 C1 Can reduce delay by more than
20%
 Technique 2 : input Reordering
Input re-ordering
when not all inputs arrive at the same time
In1 Ciritcal Signal
Assume In1 arrives much later than In2 and in3
critical path critical path

charged 01
In3 1
M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
01

delay determined by time to delay determined by time

discharge CL, C1 and C2 to discharge CL
Technique 3 : Logic Restructuring

F = ABCDEFGH
 NAND Gate

1250
quadratic
1000 function of
fan-in
750
tp (psec)

tpHL tp
500

250 tpLH
linear
0 function of
2 4 6 8 10 12 14 16 fan-in
fan-in

Gates with a fan-in greater than 4 should be avoided.

 Delay for Combinational Networks
Size each of the gates for minimum delay

1 c
a b
Cg1 CL = 5cg1
An inverter chain has three CMOS inverters. The first inverter is
unit sized and has input capacitance of 3Cg. The final (third)
inverter has a load capacitance of 81Cg. To achieve minimum
delay find sizing of two remaining inverters.

Resolve assuming first inverter drives two similar inverters

and second inverter drives two similar inverters.
 Dynamic CMOS
Tri state circuit
En controls the output
If En = 1, the output depends upon input
Else output = Z

Clocked CMOS
Also called C2MOS
En is replaced by clock
Examples of clocked CMOS circuits
Leakage determines the maximum clock frequency
 Dynamic CMOS logic
Uses clocking and charge storage properties
Clock provides synchronization
It requires fewer transistors
Based on CLK signal, it has two modes of
operation in every cycle
When CLK = 0, it is in precharge state
The output voltage drops due to leakage
(charge sharing)
 CKV

Dynamic Logic: Reading Assignment

Next class: Timing Analysis

 CKV

Thank You