Computer Architecture: A Constructive

Approach

Sequential Circuits

Arvind
Computer Science & Artificial Intelligence Lab.
Massachusetts Institute of Technology

Revised February 21, 2012

(Slides from #16 onwards)

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-1

 Combinational circuits
Sel Sel lg(n)
lg(n)
A0 O0
.. O1

Demux
A1 .. O A
. Mux .
An-1 On-1

OpSelect
- Add, Sub, ...
O0 - And, Or, Xor, Not, ...
..
Decoder

O1 - GT, LT, EQ, Zero, ...

A
lg(n)
. A
Result
On-1 ALU
Comp?
B

Such circuits have no cycles (feedback) or state

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-2

 A simple synchronous state
element
Edge-Triggered Flip-flop
D
ff Q
C

C
D
Q
Metastability

Data is sampled at the rising edge of the clock

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-3

 Flip-flops with Write Enables
EN

D D
Q ff Q
ff EN
C C
dangerous!

EN
C
EN
0
D D 1 Q
ff
Q C

Data is captured only if EN is on

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-4
 Registers
D D D D D D D D

En
C ff ff ff ff ff ff ff ff

Q Q Q Q Q Q Q Q

Register: A group of flip-flops with a common

clock and enable

Register file: A group of registers with a common

clock, input and output port(s)

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-5

 Register Files
Clock WE

ReadSel1 ReadData1
Register
ReadSel2 ReadData2
file
WriteSel
WriteData
2R + 1W

RSel1
WSel C WData

RData1
register 0
WE RSel2

register 1
RData2

No timing issues in reading a selected register

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-6
 Register Files and Ports
WE

ReadSel1 ReadData1
Register
ReadSel2 ReadData2
file
WriteSel
WriteData 2R + 1W

WE

ReadSel ReadData
R/WSel Register R/WData
file
1R + 1R/W

Ports were expensive multiplex a port for read & write

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-7

 We can build useful and
compact circuits using
registers
Example: Multiplication by
repeated addition

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-8

 Multiplication by repeated
addition
b Multiplicand 1101 (13) a0 m0
a Muliplier * 1011 (11)
a1 m1
1101
0
+ 1101
+ 0000 add4
+ 1101
a2 m2
10001111 (143)

add4

a3 m3
mi = (a[i]==0)? 0 : b;

add4

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-9

 Combinational 32-bit multiply
function Bit#(64) mul32(Bit#(32) a, Bit#(32) b);
Bit#(32) prod = 0;
Bit#(32) tp = 0;
for(Integer i = 0; i < 32; i = i+1)
begin
Bit#(32) m = (a[i]==0)? 0 : b;
Bit#(33) sum = add32(m,tp,0);
prod[i] = sum[0];
tp = truncateLSB(sum);
end
return {tp,prod};
endfunction

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-10

 Design issues with
combinational multiply
Lot of hardware
32-bit multiply uses 31 addN circuits
Long chains of gates
32-bit ripple carry adder has a 31 long
chain of gates
32-bit multiply has 31 ripple carry adders in
sequence!

The speed of a combinational circuit is

determined by its longest input-to-output
path

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-11

 Expressing a loop using
registers
function Bit#(64) mul32(Bit#(32) a, Bit#(32) b);
Bit#(32) prod = 0;
Bit#(32) tp = 0;
for(Integer i = 0; i < 32; i = i+1)
begin
Bit#(32) m = (a[i]==0)? 0 : b;
Bit#(33) sum = add32(m,tp,0);
prod[i] = sum[0];
tp = truncateLSB(sum);
end
return {tp,prod};
endfunction
Need registers to hold a, b, tp prod and i

Update the registers every cycle until we are done

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-12
 Expressing a loop using
registers
for(Integer i = 0; i < 32; i = i+1)
begin
let s = f(s);
end
return s;

s0
f +1

s i (init 0)

<32

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-13

 Sequential multiply
Reg#(Bit#(32)) a <- mkRegU();
Reg#(Bit#(32)) b <- mkRegU();
state
Reg#(Bit#(32)) prod <-mkRegU(); elements
Reg#(Bit#(32)) tp <- mkRegU();
Reg#(Bit#(6)) i <- mkReg(32);

rule mulStep if (i < 32);

Bit#(32) m = (a[i]==0)? 0 : b;
Bit#(33) sum = add32(m,tp,0); a rule to
describe
prod[i] <= sum[0]; dynamic
tp <= sum[32:1]; behavior
i <= i+1;
endrule
So that the rule wont
fire until i is set to
some other value
February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-14
 Dynamic selection
requires a mux
i

a[i]
a

>>

a
0 a[0],a[1],a[2],

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-15

 Replacing repeated
selections by shifts
Reg#(Bit#(32)) a <- mkRegU();
Reg#(Bit#(32)) b <- mkRegU();
Reg#(Bit#(32)) prod <-mkRegU();
Reg#(Bit#(32)) tp <- mkRegU();
Reg#(Bit#(6)) i <- mkReg(32);

rule mulStep if (i < 32);

Bit#(32) m = (a[0]==0)? 0 : b;
a <= a >> 1;
Bit#(33) sum = add32(m,tp,0);
prod <= {sum[0], (prod >> 1)[30:0]};
tp <= sum[32:1];
i <= i+1;
endrule

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-16

 Sequential Multiply
bIn
aIn
s1 b

&&
0
0 s1
<<
+1
<<
add

s1 s1 32:1 0
31 [30:0]

i a tp prod
s2 s2 s2 s2
31:0 0

== 32

done
result (high) result (low)

s1 = start_en
s2 = start_en | !done
February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-17
 Multiply Module
Int#(32)
Int#(32)

start
en

Multiply
rdy

module
implicit
conditions Int#(64)

result
rdy

interface Multiply;
method Action start (Int#(32) a, Int#(32) b);
method Int#(64) result();
endinterface

Many different implementations can provide the same

interface: module mkMultiply (Multiply)

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-18

 Multiply Module
module mkMultiply32 (Multiply32);
Reg#(Bit#(32)) a <- mkRegU();
Reg#(Bit#(32)) b <- mkRegU();
Reg#(Bit#(32)) prod <-mkRegU(); State
Reg#(Bit#(32)) tp <- mkRegU();
Reg#(Bit#(6)) i <- mkReg(32);
rule mulStep if (i < 32);
Bit#(32) m = (a[0]==0)? 0 : b;
Bit#(33) sum = add32(m,tp,0); Internal
prod <= {sum[0], (prod >> 1)[30:0]}; behavior
tp <= sum[32:1]; a <= a >> 1; i <= i+1;
endrule
method Action start(Bit#(32) aIn, Bit#(32) bIn)
if (i == 32);
interface
External

a <= aIn; b <= bIn; i <= 0; tp <= 0; prod <= 0;

endmethod
method Bit#(64) result() if (i == 32);
return {tp,prod};
endmethod endmodule
February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-19
 Module: Method Interface
bIn
aIn s1 b
aIn
bIn
start

en
s1 &&
rdy
0
0 s1
<<
+1
<<
add

s1 s1 32:1 0
31 [30:0]
result

result i a tp prod
rdy s2 s2 s2 s2
31:0 0

== 32 result (high) result (low)

done

s1 = start_en
s1 OR s2
s2 = start_en | !done

February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-20

 Polymorphic Multiply
Module
n
Int#(32)n
Int#(32) n could be

start
enab Int#(32),

Multiply
rdy

module
Int#(13), ...
implicit Tadd(n+n)
conditions Int#(64)

result
rdy
#(Numeric type n)

interface Multiply;
n n
method Action start (Int#(32) a, Int#(32) b);
TAdd#(n,n)
method Int#(64) result();
endinterface

The module can easily be made polymorphic

January 11, 2012 http://csg.csail.mit.edu/SNU L02-21

 Sequential n-bit multiply
module mkMultiplyN (MultiplyN);
Reg#(Bit#(n)) a <- mkRegU();
Reg#(Bit#(n)) b <- mkRegU();
Reg#(Bit#(n)) prod <-mkRegU();
Reg#(Bit#(n)) tp <- mkRegU();
Reg#(Bit#(Add#(Tlog(n),1)) i <- mkReg(n);
nv = valueOf(n);
rule mulStep if (i < nv);
Bit#(n) m = (a[0]==0)? 0 : b;
Bit#(TAdd#(n,1)) sum = addn(m,tp,0);
prod <= {sum[0], (prod >> 1)[(nv-2):0]};
tp <= sum[n:1]; a <= a >> 1; i <= i+1;
endrule
method Action start(Bit#(n) aIn, Bit#(n) bIn) if (i == nv);
a <= aIn; b <= bIn; i <= 0; tp <= 0; prod <= 0;
endmethod
method Bit#(TAdd#(n,n)) result() if (i == nv);
return {tp,prod};
endmethod endmodule
February 15, 2012 http://csg.csail.mit.edu/6.S078 L3-22