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Processes
ChemE
Electronics Physics
Chip
Material Science Manufacturing Economics
10000 ft view
Focus on the processes
Learn / Revise EE, optics, Material Science
Touch of economics
Few analytical techniques routinely used in semiconductor industry
Course Overview
Need:
Memorize (substitute for experience gained by operating
the tools yourself)
Follow in journals and internet, to keep up to date
(Information is new and the text books are not up to date in
many aspects).
Quiz: 2*15 = 30
End Sem: 40
Project: 30
PROJECT WILL BE EVALUATED ONCE IN THE MIDDLE OF THE PROJECT. AND
THEN AT THE END.
Index
Overview
Relevance, compare with traditional ChemE process
Opportunities
Course Overview
Goal, what is expected of you
Quiz, assignment etc
Scope
Outline of the course, what is covered, what is not
References
Introduction
Chip manufacturing: Snap shot
R C
Quality Control
Scope
Types of chips
CMOS BiPolar
Cu
Silicon di Oxide
General Processes Grouping
Strategy
Define shape
May change...
About 3 weeks for BEOL, 3 weeks for FEOL
General Information
Complete chip production (IDM)
Electrical Design - Some companies in India (Fabless)
Physical Layout - Need interaction with Fab
Chip production - Not much in India (Fab/Foundry)
Testing - either at the customer site or at the production site
Chip production
Needs huge investment & state of the art tools
Work force
Discipline, for mass production (1 lot == 1 Million USD ==
80 kg gold)
General Information
Chip production in India
Semiconductor Complex Limited (SCL), Chandigarh
DRDO,ISRO may have their own facilities
BEL???
0.8 m, Aluminum, 2 metal layers
International Tech Node
SCL
Minimum Feature Size (um)
0.1
Smaller node earlier means
more advanced technology
0.01
90
92
94
96
98
00
02
04
19
19
19
19
19
20
20
20
Year
General Information
Processor Chips
Process variations
Chip Speed variations
Same design, production line, wafer --> Different chips
Memory chips
Repetitive design
Easier production --> lower cost
Processes
Visualize the Final Product
Focus on
The parts that need to be made
The processes (for each of the part)
Finally,Focus on integrating the processes
Chip Xsection- Simplified
Schematic
Wiring Metal connectors
Insulator
? ?
Silicon Wafer
Chip - Simplified Schematic
Silicon Wafer
Level 1
Silicon Wafer
IBM
FEOL Processes
Shape Definition
Photo Lithography
Modification
Ion Implantation
Diffusion
Rapid Thermal Anneal (RTA)
Oxidation
Deposition
Chemical Vapor Deposition (CVD)
Physical Vapor Deposition (PVD)
Removal
Chemical Mechanical Polishing (CMP)
Etching
BEOL Processes
Shape Definition
Photo Lithography
Modification
Anneal
Deposition
Chemical Vapor Deposition (CVD)
Physical Vapor Deposition (PVD)
Electrochemical Deposition
Removal
Chemical Mechanical Polishing (CMP)
Etching
Appendix
Acronyms
CMP - Chemical Mechanical Polishing
CVD - Chemical Vapor Deposition
PVD - Physical Vapor Deposition
SEM - Secondary Electron Microscopy
EDX - Energy Dispersion X-Ray Analysis
TEM - Transmission Electron Microscopy
Acronyms
IC - Integrated Circuits
ASIC - application specific integrated circuit
GaAs - Gallium Arsenide device
FEOL - Front End of the line (processes up to making the device)
BEOL - Back end of the line (processes involved in creating the
wiring connections between the devices)
Acronyms
CMOS Complementary metal oxide semiconductors
VLSI -Very large scale integration (creating one chip with many
millions of devices)
ULSI - Ultra large scale integration ( billion devices)
ALD - Atomic Layer Deposition (Depositing one layer of atoms in a
controlled manner)
MBE - Molecular Beam Epitaxy (Targetted layer by layer growth of
material)