NMOS NOR:

VDD

vout
VOUT

A B
A B
GND
CMOS NOR: VDD

VDD

A A
VOUT
vout B

A B

GND

GND
CMOS INVERTER:
VDD
VDD

Vin VOUT
vout
Vin

GND
GND
 CMOS NAND: VDD
VDD

B
A
VOUT vout
A
B

GND
GND
 NMOS TRANSISTORS FORMED BY OVERLAPPING THE POLY SILICON LAYER
WITH DIFFUSSION LAYER

N-DIFF S
S
L:W
L:W
G G

POLY D D

S S
L:W L:W
G
G
IMPLANT
D
D
 NMOS Inverter:
VDD
VDD

VOUT
VOUT

VIN
VIN

GND GND
NMOS NAND:
VDD VDD

VOUT
VOUT
A
A

B
B
GND
GND
 NMOS NOR:
VDD VDD

VOUT
VOUT

A B A B

GND
GND
NMOS NAND:
VDD
VDD

VOUT
VOUT
A A

B B

C
C

GND GND
 CMOS INVERTER:
VDD VDD

Vin VOUT Vin VOUT

GND
GND
CMOS NOR:
VDD
VDD
A

A
B
VOUT B

A B

GND
GND
CMOS NAND:
VDD VDD

A B A
VOUT

A VOUT B

GND
GND
CMOS Logic:
VDD

A
c

B
GND
PMOS Inverter:
VDD VDD

Vin Vin

VOUT
VOUT

GND
GND
PMOS Logic:
VDD

Vout = (A.B)+C A B

VOUT
NMOS Inverter:

VDD

vout

VOUT

vin
VIN

GND
NMOS NAND:
VDD
VDD

vout
VOUT
A A

B B
GND
GND
 CMOS NOR: VDD

VDD

A
A
VOUT B vout B

GND

GND