ZXG10 iBSC Introduction

Course Objectives

 After learning this course, you will:

 Understand the functions, features and specifications
of ZXG10 iBSC
 Master the hardware structure of ZXG10 iBSC and the
working principles of its shelves and boards
 Master the interface design and logical units of ZXG10
iBSC
 Master signal streams on the control plane and the
user plane of ZXG10 iBSC
 Master the internal cable connections of ZXG10 iBSC
Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
Network Structure
MSC/VLR GMSC

Nc
A
BTS PSTN
Mc
BSC

BTS
Inter-PLMN
Gb Nb
Iur-g
MGW GMGW

IuCs
NodeB

RNC IuPs

NodeB
SGSN GGSN
What does "i" stand for?

intelligent integration
intelligent identification of wireless integrates multi-interfaces
access intelligent error E1/STM-1/IP integrates multi
self-correction transmission supported

immensity intensify
large capability intensified design
supports 3072 TRX and 15000 Erl supports FR/EFR/HR/AMR/WB-AMR,
with only two racks innovative NetSpeed wireless
enhanced technology

IP
All-IP platform
supports IP bearer
ZXG10 iBSC Product Features
 Based on V3 universal hardware platform
 All IP hardware architecture
 Large capacity and strong processing
capabilities
 Modular design with good scalar
 Separation of control streams from media
streams
 Supporting Flex A and Flex Gb
 Coding scheme: FR/HR/EFR/FR-ARM/HR-
AMR
 Transmission interface: E1/T1/FE/STM-1
 Easy and smooth upgrade
 Flexible networking modes
 High integration and low power consumption
Universal All IP Hardware Platform

GSM / WCDMA TD-SCDMA

Universal
Hardware Platform
Totally 16 boards

Smooth
All IP Upgrade
CDMA 2000 NGN Modularity
Modular Design

 Boards
 Different software can be used to define
different functions for the same board.
 AIU, BIU, PCU and TCU are logical units; All
interface units are in the resource shelf.

 Easy Scalability BGSN BGSN BGSN

 The system can be BCTC BCTC BGSN

expanded via adding

BGSN BGSN BGSN
RCBUs.
 3 RCBUs/2 racks. BPSN BPSN BGSN

RACK1 RACK1 RACK2

Multiple Access Modes and Smooth Evolution
 iBSC supports multiple access modes
 E1/T1
 STM-1
 FE/GE
 Evolution
Advantages
• Saves 20% space when 2G and 3G
iBSC iBSC iBSC modules are integrated into the same
site.
RNC RNC&BSC • Shares cabinets, spare parts,
BSC RNC RNC&BSC transmission and OMM.
BSC BSC RNC&BSC • Saves power consumption
• Saves engineering and network
BSC BSC RNC&BSC
upgrade cost
ZXG10 iBSC Interfaces

Logical
No. Link Object Interface Type
Interface
1. A MSC STM-1, E1, FE/GE

2. Gb SGSN E1, FE/GE

3. Abis BTS E1, STM-1, FE/GE
4. Ater iTC STM-1, E1
 ZXG10 iBSC Interface Specifications
A-Interface E1(T1) A STM-1 A IP A

Number
Abis Number of Interface Number of
Cabinet of Interface Capacity Interface Capacity
Interface Carriers Capacity Carriers
Carriers
A Single Abis:208 E1(T1) Abis:208 E1(T1) Abis:208 E1(T1)
1024 1024 1024
Cabinet A:188E1(T1) A:4 pairs of STM-1 A:1 pair of GE
E1(T1) Abis
Abis:624 E1(T1) Abis:624 E1(T1) Abis:624 E1(T1)
Dual Cabinets 3072 3072 3072
A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE
Abis:3 pairs of
A Single Abis:3 pairs of STM-1 Abis:3 pairs of STM-1
1024 STM-1 1024 1024
Cabinet
A:188E1(T1) A:4 pairs of STM-1 A:1 pair of GE
STM_1 Abis
Abis:9 pairs of
Abis:9 pairs of STM-1 Abis:9 pairs of STM-1
Dual Cabinets 3072 STM-1 1024 3072
A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE

A Single Abis:1 pair of GE Abis:1 pairs of GE Abis:1 pair of GE

1024 1024 2048
Cabinet A:252E1(T1) A:4 pairs of STM-1 A:1 pair of GE
IP Abis Abis :2 pairs of
Abis:2 pairs of GE Abis:2 pairs of GE
Dual Cabinets 3072 GE 3072 3072
A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE

A Single Abis:160 E1(T1) Abis:160 E1(T1) Abis:160 E1(T1)

1024 1024 1024
Cabinet A:188E1(T1) A:4 pairs of STM-1 A:1 pair of GE
IPoE Abis
(EIPI+DTB) Abis:480 E1(T1) Abis:480 E1(T1) Abis:480 E1(T1)
Dual Cabinets 3072 3072 3072
A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE

A Single \ Abis:3 pairs of STM-1 Abis:3 pairs of STM-1

IPoE Abis \ 1024 1024
Cabinet \ A:4 pairs of STM-1 A:1 pair of GE
(EIPI+SDTB2)
Dual Cabinets \ \ 3072 11 pairs of STM-1 3072 A:2 pairs of GE
ZXG10 iBSC Physical Specifications
Item Specification
Dimensions (H*D*W) (mm) 2,000 * 800 * 600
<270Kg(1 rack)
Weight
<540Kg(2 rack)
All E1:
2,558W per rack, 6,368W/2
racks
Power Consumption
All IP:
2,542W per rack, 3,808W/2
racks
Power Source Requirements -48V DC (-40V DC to -57V DC)
Long-term temperature: 0°C–
40°C.
Operating Temperature
Short-term temperature: -
5°C–45°C.
Long-term humidity: 20–90%.
Operating Humidity:
Short-term humidity: 5%–95%.
ZXG10 iBSC Performance Specifications
Item Specification
BHCA 4,200K

Maximum traffic 15000 Erl

Maximum throughput over Gb E1 Gb: 256Mbps

interface IP Gb: 600Mbps
One Rack: 1,024
Maximum TRXs supported
Two Rack: 3,072

 The all-IP architecture conforms to the trend towards an IP-

based network
 Large capacity and strong processing capabilities
 Supports E1, T1, STM-1 and IP interfaces and flexible
networking modes
Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
Hardware Architecture Introduction
 Work Planes
 Control Plane & User Plane

 Major Interfaces
 Abis – IP over E1, E1, IP
 A – TDM (E1, STM-1), IP
 Gb – TDM (E1), IP
 (Ater)

 Levels of Shelves Shelf Types

 Control shelf (BCTC), resource shelf (BGSN), switch shelf
(BPSN)

 Boards
ZXG10 iBSC Shelves
Control Shelf (BCTC)
System control and management
(BGSN)
Resource Shelf Clock capture and distribution

Processing of control plane signaling

(BCTC)
System operation and maintenance
Control Shelf

Resource Shelf (BGSN)

(BGSN) System external access
Resource Shelf
Processing of universal services

(BPSN)
Switch Shelf
Switch Shelf (BPSN)
Large-capacity IP switch platform on the user plane
ZXG10 iBSC Boards
Shelf Board Full Name Functions
Universal Interface Module for
UIMC Level 2 switch of control plane signaling
Control plane
Control and management of CS and PS services, processing of
CMP Control Main Processor BSSAP and BSSGP protocols, and resource management of the
system
CHUB Control HUB Switch and convergence of control plane signaling
BCTC
Operation and maintenance, system control, management and
OMP Operation Main Processor
monitoring
SBCX X86 Single Board Computer O&M server
CLKG Clock Generation Clock generation and distribution
ICM Integrated Clock Module Clock generation and distribution (with GPS)
GLI Gigabit Line Interface Level 1 switch, interface with the resource shelf
BPSN Provides bi-directional user plane data switch with a capacity of 40
PSN Packet Switch Network
Gbps on each direction
Signaling processing, interface board (16 E1 lines for A/Gb,
SPB2 Signaling Processing Board
eight E1 lines for Abis)
Level 2 switch between the control plane and the user plane,
GUIM Giga bit User Interface Module
resource shelf management
GUP2 GSM Universal Processing Processing of user plane protocols, such as TC, PCU and RTP
BGSN
DTB Digital Trunk Board Provides 32 E1/T1 trunk interfaces
SDTB2 Sonet Digital Trunk Board 2 Provides two STM-1 interfaces
GIPI GE IP Interface Provides four FE interfaces or one GE interfaces for Abis/A/Gb
EIPI E1 IP Interface provides E1 or T1 based IP connection
Physical and Logical Boards of ZXG10 iBSC
Physical
Logical Board Functions
Board
Completes IP access over the Abis interface, and sever the control
IPBB
plane from the user plane
Completes IP access over the A interface, and sever the control
GIPI IPI
plane from the user plane (signaling from service)
Completes IP access over the Gb interface, and sever the control
IPGB
plane from the user plane
Search 20 ms TRU frames according to the channels and form IP
BIPB2 packets
For IP access over the Abis interface, it also processes RTP.

GUP2 AIPB It processes RTP and forms IP packets

UPPB2 User plane protocol processing in the PS field

Completes the transcoding and rate adaptation of TRAU frames, and
DRTB2
provides FR, EFR, AMR and TFO functions

LAPD2 LAPD signaling processing

SPB2 SPB2 MTP2 protocol processing

Provides Gb interface functions, and processes the FR, NS and

GIPB2
partial BSSGP of GPRS.
Introduction to BCTC
 Completes the global operation Control Shelf

and maintenance of the 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

system, provides the global

Rear Board
R R R R R R R R
R R
U U M M C C C C
S S
system clock, manages the V V
I I
M M
P
B
P
B
K K
G G
H
B
H
B
B B
2 3 1 2 1 2
control plane, and responsible
for the switch between the BCTC

control plane and the Ethernet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Front Board
S S U U C C
 Each iBSC must be configured C C
M M
C
M
C
M B B I I
O
M
O
M
I I
C C
H H
C C M M U U
P P P P P P M M
with one control shelf, which is X X C C B B

located in Shelf 2 in Rack 1

No. Board Name Number Slot No. Backup
1 OMP 2 11–12 1+1
2 CMP 2~4 1~4 1+1
3 CHUB 2 15~16 1+1
4 ICM 2 13~14 1+1
5 UIMC 2 9~10 1+1
6 SBCX 2 5，7 1+1
BCTC Working Principles
BPSN BGSN
 The clock generation board
(ICM) distributes clock signals to UIMC GUIM
the switch shelf and resource
shelves through cables. 8K/16M

 OMP and SBCX boards are CHUB UIMC ICM

connected to the iOMCR
through the hub to sever intranet
Ethernet
segments from Internet
segments.
CMP OMP SBCX
 The CHUB acts as the control BCTC
stream convergence center for
the control streams from the
switch shelf, the resource shelf
HUB HUB
and the control shelf.
Outside
network
Introduction to BGSN
Gigabit Resource Shelf
 Provides system external 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
interfaces.

Rear Board
R R R R R
R R
S D S G G
D S
 Processes universal services. P T P U
M
U
M
T P
B B B B B
1 2
 Acts as the Level 2 switch
BGSN
center.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
 The BGSN is configured in

Front Board
G S S G G G D E G S
D P U U
U P U I U P
Shelf 1 and Shelf 3 of the P B
T
B
B P I I
T
B P P B
2 2 2 2 M M I 2 2
main rack. When a single
shelf constitutes an office, it is
configured in Shelf 2.
No. Board Name Number Slot No. Backup
1 GUIM 2 9~10 1+1
2 GIPI - 1-8,11-17 1+1
3 GUP2 - 2-8,11-16 -
4 DTB 0-8 1-8,11-14,17 -
5 SDTB2 - 1-8,11-16 1+1
6 SPB2 - 1-8,11-17 -
7 EIPI - 1-8,11-17 -
BGSN Working Principles
 The GUIM board is the
convergence and switch center for BPSN BCTC
various data in the resource shelf. It
completes the information exchange GLI CHUB ICM
between modules.
 The GUIM board interconnects with
the GLI board in the packet switch BGSN
shelf to carry out level 1 switch GUP2 GUP2 GUIM
between different resource shelves.
 DTBs and SPBs provide E1
interfaces, and SDTBs provide
STM-1 access.
 GIPI boards provide FE and GE SDTB 2 DTB SPB2 GIPI
access.
 Processes universal services STM-1 E1 E1 FE GE
(conversion from TC and TDM to IP
packets, processing of user plane
protocols).
Introduction to BPSN
 Interconnects BGSNs and Packet Switching Shelf

Level 1 switch centers on the 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

user plane.

Rear Board
R R
U U
I I
 Each iBSC should have one M M
2 3
BPSN, which is configured in
BPSN
Shelf 4.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
 If the iBSC has two BGSNs,

Front Board
G U U
C C C C
then the BPSN is not G
L
G
L
G
L
G G
L L L
P
S
P
S M M M M I
M
I
M
I I I I I I N N P P P P
mandatory. However, this can C C

affect the capacity expansion

of the system.
No. Board Name Number Slot No. Backup

1 PSN 2 7~8 Load sharing

2 GLI 2~6 1~6 Load sharing
3 CMP 0~2 11~14 1+1

4 UIMC 2 15~16 1+1

BPSN Working Principles

 The GLI board receives user BPSN BCTC

FE
plane data from the GUIM PSN UIMC CHUB
board.
 The PSN provides 40Gbps LVDS
data switch capacity. GLI ...... GLI ICM
 The UIMC receives clock
and control signals from the fiber
control shelf and distributes
control & management GUIM GUIM
interfaces and clock signals
in the shelf. BGSN BGSN
Shelf Configuration (1)
PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
BIU G G S S R R R R
S G D D D G D D G G D D G S S R R R R R R G G SR R R R R R
U U P P S D D
P U U I I T T U P P S D D D D D U U PG G S S
T T T T T I B B P T
B I P P T M M BE E T
AIU P
B B B
P
B B 2 2 B B P B B P T T T T B
P P
M M I I
2 2 2 / / 2 2 2 B B B B B B 1 2 /R /
R B B B B
PCU
U O C C R R R R R R R R R
C C C C S S U R
TCU M
P
M M M
P P P
B
C
B
C
I
M
I
M M
O
M
I
C
M
I
C
M
H
U
H
U
S
V
S
V
U U M
I I P
M M
M
P
C
K
G
C
K
G
C
H
B
C
H
B
Abis Interface E1
X X C C P P B B B B 2 3 B B 1 2 1 2
FAN FAN
R R
S G G D D G D D G G D G D D G G S R R R R R R R R R
P U U U U U U U U P D D D D G G D D D S
T T T S
B P P T T P T T I I P P P B P T T T T U U T T T P
B B B M M
2 2 2 B B 2 B B M M 2 2 2 2 B B B B B B B B B
1 2
G G G G G G P P C C U U R R
U U
A-Interface E1
L L L L L L S S M M I I
M M I I
I I I I I I N N P P M M
C C 2 3
FAN FAN

PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
G G R R R R
S G D D D G D D S S S G S R R R R R R G R R R
P U U U U D P P P U P S D D D D D U
G D S S S S
T T T T T
B P P I I T B B B P B P T T T T T
U T P P P P
B B B B B M M B M M
2 2 2 2 2 2 2 2 B B B B B B 1 B B B B B
2
R R
D G G D D G D D G G D G D D G G D R R R R R G G R R R R
U U U U U U U U D D D D D U U D D D D
T P P T P T
T P T T I I T P T T P T T T T T M M
T T T T
B 2
2 B B 2 B B M M B 2 B B 2 2 B B B B B B 1 2 B B B B
FAN FAN
R R
S G D D D G D D G G D S S G S R R R R R R R R R R
P U U U U P U P D D D D G G D
T P S D S S S
B P T T T P T T I I B B P B P T T T T T U U T P P P
B M M
2 2 B B B 2 B B M M 2 2 2 2 B B B B B B B B B B
1 2
R R
D G G D D G D D G G G D D G G D R R R R R G G R R R R
D D
U U U U U U U U D D D D D D D D
T P U U
P T T P T T I I T P T T P P T T T T T T
M M
T T T T
B 2
2 B B 2 B B M M B 2 B B 2 2 B B B B B B 1 2
B B B B

FAN FAN
Cabinet Configuration (2)
PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
G G R R R R
G G G G G G G G G G G R R
BIU U U U U U G G M M
I I U U I I U U G G
P P P P P P I I P P P E E U U I I
P P
2 2 M M M M N N
I I 2 2 2 I I 2 2 R R
AIU 1 2 C C
R R R R R R R R
C C C C S S U U O O I I C C R R
PCU B I I H H S S U U M M C C C C
M
P
M M M
P P P
B
C C M M M M C
C C P P M
C
M
U U V V I I P
M M
P K
G
K
G
H
B
H
B Abis Interface IP
TCU
X X B B B B 2 3 B B 1 2 1 2
FAN FAN
R R
G G G G G G G G G G G G G G R R R R R R
G G G G
I I U I I U U U U U I I U U G G G G
P P P I P P P E E U U E E
P P P I P P P E E
M M
I I 2 I I 2 M M 2 2 I I 2 2 R R R R R R
1 2

G G G G P P C C U U
I I
R R
U U
A-Interface IP
L L L L S S M M
M M I I
I I I I N N P P M M
C C 2 3
FAN FAN

PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN

G G G G G G R R R
G G G R
I I U U U U U U G G G G
U
P P P P P I I P P E E U U
I 2 2 M M 2 2 R R M M
I 2
1 2

FAN FAN

FAN FAN
Cabinet Configuration (3)
PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN

E D E G D G G SG S G R R R R
D D D S G G G R R R R R G G SR SR R
U U PI PI P U U D D D D U U PG G S
I
BIU P T T I T T U T
I B B U D P
I P P B P P P T T T T T M M BE E P
B B P B B P B 2 2
M M I I B
I I 2 / / 2 2 2 2 B B B B B 1 2 / R /
R B
AIU
R R R R R R R R
C C C C S S U U O I C C R R
PCU
M
P
M M M
P P P
B
C
B
C
I I
M M M
O
M
I

M M
H
C C U
H
U
S
V
S
V
U U M
I I P
M M
M
P
C
K
G
C
K
G
C
H
B
C
H
B
Abis Interface IPoE
TCU X X C C P P B B B B 2 3 B B 1 2 1 2
FAN FAN

G G G G G G R R R R R R R R
G G G G G G G G G
I I I I U U I I G G G G G G G G
U U U U U U U
P P P P I I P P E E E E U U E E
P P P P P P P
M M I I R R R R M M R
I I I I 2 2 2 2 2 2 2 R
1 2
G G G G G G P P C C U U R R A-Interface IP
I I U U
L L L L L L S S M M
M M I I
I I I I I I N N P P M M
C C 2 3
FAN FAN

PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
G G R R R
E D D E D D G D S S S G G G R R R R R G G
R R
U U P U U D D D D S S S
I T T I T T U T
I I B
P P U D U U P P
B B P P P T T T T T P
P B B P B B P B
M M 2 M M B
I I 2 2 2 2 2 2 B B B B B B B
1 2
E D D E D D G D G S S G G G R R
G R R R R R R R
P P U U U G G
I T T I T T U T U U D D D D D S S
I I B B P P P T U U P P
P B B P B B P B T T T T
M M
I I 2 M M 2 2 2 2 2 B B B B B B B
1 2
FAN FAN

FAN FAN
Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
OMP
 The OMP board processes the global procedure,
performs O&M related control of the entire system
(including O&M proxy), and connects to the OMM
through the 100M Ethernet.
 As the processing core of iBSC operation &
maintenance, the OMP board can directly or indirect
monitor and manage all boards in the system. It
provides two links (Ethernet interface and RS485) for
configuration management of system boards.
 OMP
 CPU A is responsible for global operation & maintenance.
 CPU B is the Router Processing Unit (RPU).
 The HD Disk is a 2G hard disk to store system data, for example,
board software version files, configuration files and logs.
CPU B
RS485,RS232 DEBUG 2-232
RS232
RS485

CP FE

What are the CPU Core

Ethernet
OMC2

functions of the
Back Board
RPU? Logic Unit
Power
Management

RS485,RS232 GPS485
PD 485
RS232
RS232
CPU Core RS485 DEBUG1- 232
1. Enables intranet addresses within the
BSC to communicate with each other. HD Disk
OMC1
Ethernet
2. Provides routes for the operation and CP FE

maintenance of the BTS. CPU A

CMP
 The CMP board controls and manages service
calls in the PS and CS fields, and manages the
resources of BSSAP, BSSGP and the system.
 Its physical board is MPx86/2, the same as the
OMP, but the memory capacity is slightly different:
1GB/CPU for the OMP, and 2GB/CPU for the
CMP, and the OMP has a hard disk).
UIMC
 The UIMC is responsible for Ethernet Level 2 switch
within the BCTC and the BPSN and the management of
the BCTC.
 The UIMC provides the clock drive function inside the
BCTC and the BPSN. It inputs 8K and 16M signals, which
are sent to different slots in the BGSN after phase lockup
to provide 16M and 8K clocks for the boards.
 The UIMC provides management interfaces for the BCTC
and the BPSN; it also provides board resetting and
resetting signal collection functions for the BCTC and the
BPSN.
UIMC
 The UIMC provides one internal GE interface that is connected to the
CHUB.
Inner Bus

RS485
DEBUG 232
Logic Unit Clock Unit CPU DEBUG FE

Inner Bus
Back Board

CP FE, CP GE CLKIN

User Plane Control Plane CP FE 1~10

Switch Switch

Ethernet
Switch Unit
CHUB
 The CHUB works together with the UIMC/GUIM to be
responsible for control plane data stream exchange and
convergence in the system.
 The control plane data from each shelf is sent to the
Ethernet switching unit of CHUB board through the
Ethernet cables on the control plane.
 The data is then sent to UIMC board of the BCTC
through GE for level-2 switch, and then distributed to
each CMP board for processing.
CHUB
 The RCHB1 board has three FE buses, on which FE interfaces are grouped as
FE1–8, FE9–16 and FE17–24.
 The RCHB2 board has three FE buses, on which FE interfaces are grouped as
FE25–32, FE33–40 and FE41–46.

DEBUG FE/232
Logic Unit CPU

Inner Bus
Back Board

CP GE
Ethernet Ethernet
Switch Switch

Ethernet
Switch Unit

FE1 FE1 FE1 FEn

ICM
 Responsible for system clock supply and external
synchronization. The board extracts clock reference via
the A interface and drives multiple channels of clock
reference signals for use by each interface unit.
 It receives GPS satellite signals and extract 1PPS signals
and related TOD messages. The 1PPS signals are used
as reference for phase lockup in order to create
PP2S,19.6608MHz and 8 K clock references for iBSC.
 Supports background or manual selection of clock
references, including BITS, line (8 K), GPS, local (Level 2
or Level 3); supports software shielding of manual
switchover.
 Supports four work modes: CATCH, TRACE, HOLD and
FREE.
ICM
 8 K reference input，when DTB/SDTB2 provides the clock reference, it
connects with the 8KOUT/DEBUG-232 interface of RGIM1.When SPB2
provides the clock reference, it connects with the 8KOUT/CPU1-RS232
interface of RSPB.
 One CLKOUT interfaces outputs a one-to-six cable; one shelf has two
UIM/GUIM boards with two clock sockets, so one CLKOUT interface can
connect with three shelves. The RCKG1 board has two CLKOUT interfaces
providing six clock output lines, that is , it can connect with six shelves.
GPS
8KIN
Reference GPS Unit
2Mbps/2MHz Selection Unit
PP2S/16CHIP
8K ,16M , 32M , 64M
PLL Unit
CLKOUT
Oscillastor

RS232
CPU
RS485

Inner Bus
SBCX
 The SBCX board is the server board. It mounts the server
on the rack.
 It provides the keyboard, the mouse and the VGA interface.
 Uses Sossaman dual-path dual-core CPU with a frequency
of 2G Hz.
 Supports multiple operating systems, including Windows
XP/2000/2003, Linux and Solaris.
 Provides three FE interfaces, two GE interfaces and one
RS232 serial port.
 Provides four universal USB interfaces.
 Supports boot from hard disk and boot from USB drive.
SBCX
 OMC1(eth3) is set to an external network address to communicate with
NetNumen M31 server.
 OMP1(eth6) is set to an intranet address to communicate with the
OMP. VGA
USB
CPU Outside Mouse(MS)
Dual Core Interface
KeyBoard(KB)

OMC1
OMC2
Outside OMP1
Interface
RS232
USB

SAS HD1
SAS
Controller
SAS HD2
DTB
 Provides 32 E1/T1 links for external connections.
 Supports extraction of 8K synchronization clock from the
lines, which is transferred to the ICM board through the
cable as clock reference.
 Supports 120/75 Ω impedance selection for E1 cables,
and supports coaxial cables and twisted-pair cables.
 Supports 100 Ω twisted-pair T1 cables.
DTB
8KOUT/DEBUG-232
CP FE ，RS232，RS 485
CPU

Clock
Clock Unit

Back Board
Logic Unit

E1/T1 1~32

Circuit Switch HW
Interface Unit
Unit
DTP DIP Switches

S1
ON
S2
ON
S3
ON
S4
ON
S5
ON
ON S6
S7
ON ON
S8
ON S9
S10
ON ON
S11
S12
ON

X23
 DTP DIP Switches
DIP Switch Configuration Default Location
Purpose
Switch Mode 1 2 3 4 1 2 3 4

Used to set the 75 Ω ON ON ON ON

S1~S6 resistances that match
S9 the impedances of ON ON ON ON
S12 different E1 paths to 75
120 Ω OFF OFF OFF OFF
Ω or 120 Ω.

Used for indicating the 75 Ω ON ON ON ON

receiving matching
S7
impedance of ON ON ON ON
S8
corresponding E1 chip
to the CPU. 120 Ω OFF OFF OFF OFF

SHORT
ON ON ON ON
Used for reporting the HAUL
S10 long/short wire status
ON ON ON ON
S11 of each E1 chip to the
CPU. LONG
OFF OFF OFF OFF
HAUL
RDTB Jumpers
 On the RDTB, the E1 cable
works in the 75 Ω unbalanced
coaxial transmission mode by
default.
 If the E1 line uses 120 Ω
balanced transmission mode,
the short-circuit block at X9–
X16 on the RDTB needs to be
removed.
 The sending end is grounded
through the jumper. The
receiving end is connected to
a capacitor and then grounded
through the jumper. Jumpers
X9–X16 are used to complete
such settings.
RDTB Jumpers
X9-X16 Pin Connection Definitions

1-2 Connect E1_TX（N）-R to the protection ground (Path N)

3-4 Connect E1_RX（N）-R to the protection ground (Path N)

Connect E1_TX（N+1）-R to the protection ground (Path

5-6
N+1)
Connect E1_RX（N+1）-R to the protection ground (Path
7-8
N+1)
Connect E1_TX（N+2）-R to the protection ground (Path
9-10
N+2)
Connect E1_RX（N+2）-R to the protection ground (Path
11-12
N+2)
Connect E1_TX（N+3）-R to the protection ground (Path
13-14
N+3)
Connect E1_RX（N+3）-R to the protection ground (Path
15-16
N+3)
SDTB2
 The SDTB2 acts as the digital trunk interface board. It
provides two 155M STM-1 standard interfaces.
 Supports CAS and CCS, and provides an access
processing capacity equal to 126 E1 lines or 168 T1 lines.
 Outputs one path of differential 8 K synchronous clock
signals for the reference of the clock board
SDTB2

8KOUT/DEBUG-232
CP FE ，RS232，RS 485
CPU

Clock
Clock Unit

Back Board
Logic Unit

STM-1
Circuit Switch HW
Interface Unit
STM-1 Unit
SPB2
 According to its functions, the SPB2 board can be classified into the
LAPD processing board (LAPD2), the signaling processing board
(SPB2) and the Gb interface processing board (GIPB2).
 The LAPD2 board processes LAPD signaling. LAPD signaling data
from the BTS are received by the DTB/SPB/SPB2 board, and then
switched to the LAPD2 board through the circuit switching net on the
UIM board in the local resource shelf or the GUIM board in the local
Gigabit resource shelf. The LAPD2 completes the processing of
LAPD signaling data.
 The SPB2 board processes MTP2 and X.25 protocols. It supports
extraction of 8 K synchronization clock from the lines, which is
transferred to the ICM board through the cable as clock reference.
 The GIPB2 board processes the FR, NS and partial BSSGP protocols
for the GPRS, and provides Gb interfaces.
SPB2
CPU4-RS232
CPU 4

CPU3-RS232 CP FE
CPU 3
Ethernet
Switch Unit UP FE
CPU2-RS232
CPU 2

8KOUT/CPU1-RS232
CPU 1

Back Board
RS232，RS 485

Clock
Clock Unit
Logic Unit

E1/T1 1~16

Circuit Switch HW
Interface Unit
Unit
SPB2
 Interface unit, which connects with the switching unit and
provides E1 interfaces.
 Circuit switch unit, which implements the switching
between interface unit circuits and backplane circuits.
 CPU, which implements signaling processing, board
management and internal connection control.
 Ethernet Switch Unit, which implements control plane and
user plane data switch and provides FE interfaces.
 Clock Unit, which extracts line clock signals and sends
them to the ICM board.
 Each SPB2 board contains four CPUs.
 Each SPBs board provides 16 E1/T1 interfaces.
GIPI
 The GIPI board provides IP interfaces between iBSC and
the BTS, the SGSN and the MSC/MGW.
 Implements Layer 3 protocol interface processing,
separates control plane data from user plane data, and
sends the data respectively to the Ethernet interfaces on
the internal control plane and user plane.
 According to functions, GIPI can be classified into four
functional boards:
Abis interface Gigabit IP interface board(IPBB)
A interface Gigabit IP interface board IPAB(Signaling)
A interface Gigabit IP interface board IPI （signaling and service）
Gb interface Gigabit IP interface board(IPGB)
GIPI
 The Interface Unit receives data and sends it to the service processing unit,
which separates user plane data from control plane data. User plane data is
then sent to the GUP2 through the user plane switch network, and control
plane data is sent to the CMP through the control plane switch network.
 The GIPI board can choose RGER (providing one GE interface) or RMINIC
(providing four FE interfaces) as its rear board.

Processing Unit GE1

GE2

RS232 DEBUG1-232
Back Board

CPU Interface
Unit DEBUG2-232

Logic Unit

CP FE, UP GE
EIPI
 The EIPI board provides E1 or T1 based IP connection and
works together with the DTB. It has no external interface
and no rear board. One EIPI works together with two DTBs
to provide up to 64 E1 or T1 ports.
EIPI
 The interface unit receives HW data and sends it to the HPS daughter
card. The data is then processed according to the HDLC protocol and
then sent to the service processing unit. It sends user plane data
through the user plane switch network to the GUP2 for processing, and
sends control plane data through the control plane switch network to
the CMP for processing.
HW
HPS Subcard

Processing Unit

Interface
Back Board

Unit
RS232
CPU

Logic Unit

CP FE, UP GE, HW
GUIM
 The GUIM performs Ethernet Level 2 switching between the control
plane and the user plane in the Gigabit resource shelf, the CS field
timeslot multiplexing slot switching and Gigabit resource shelf
management. It also provides external interfaces for the Gigabit
resource shelf.
 It has the capability of 16 K circuit switching, and provides an internal
circuit switching network for the GE resource shelf.
 It provides the clock drive in the resource shelf. It inputsPP2S, 8K
and 16M signals, which are sent to different slots in the resource
shelf after phase lockup to provide 16M, 8 K and PP2S clocks for
resource modules in this shelf.
 The UGIM board performs Gigabit resource shelf management and
provides RS485 management interfaces in the Gigabit resource shelf;
It also provides board resetting and in-slot signal collection functions.
GUIM
Circuit
Switch Unit

HW

Inner Bus

RS485
DEBUG 232
Logic Unit Clock Unit CPU

Inner Bus
Back Board

CP FE

CLKIN

Ethernet 4*1 Gbps optical for UP

UP GE

Switch Unit

CP FE 1~6
User Plane Control Plane
Switch Switch
GUP2
 According to functions, GUP2 boards are classified into five functional
boards: Abis interface processing board BIPB2, A interface
processing board AIPB, user plane processing board UPPB2, dual
rate transfer board DRTB2 and Ater interface processing board TIPB2.
 Over the STM-1 or E1 Abis interface, CS and PS services from the BTS
are switched to the BIPB2 board through the UIM board in the local
resource shelf or the GUIM board in the local Gigabit resource shelf. The
BIPB2 board searches 20ms TRU frames or PCU frames and form them
into IP packets, which are sent to the TCU or the UPU for processing.
Over the IP Abis interface, the BIPB2 board is also used to process RTP.
 The DRTB2 implements code conversion, finishes TRAU frame conversion
and rate adaptation, and provides FR/EFR/HR/AMR/TFO function.
 The AIPB board processes RTP and forms data into IP packets over the A
interface.
 The UPPB2 processes user plane protocols such as BSSGP, PDCP and
GTP_U under the A/Gb mode.
GUP2
 Each GUP2 board has 15 DSPs.

HW

Circuit Switch Logic Unit Clock Unit

Unit

DSP Unit

Back Board
DSP
CPU P UP GE
Ethernet
Switch Unit
…

DSP
P

CP FE
GUP2
 CPU: responsible for board management, and provides
control plane FE interfaces for external connection.
 DSP: processes universal services, including functions of
BIPB2, AIPB, DRTB2, UPPB2 and TIPB2.
 Circuit Switch Unit: connects the serial ports of multiple-
chip DSP with the circuit switching network.
 Ethernet Switch Unit: implements the Ethernet
connections for multiple-chip DSP and provides the user
plane FE interface for external devices.
 Clock Unit: provides necessary clock signals for the units
on the board.
GLI
 The GB Line Interface (GLI) board is located at level 1
switching subsystem of iBSC. It finishes physical layer
adaptation, IP package query, segmentation, forwarding,
and flow management functions, processes bi-directional
2.5Gbps forwarding, and implements the interfaces to
different resource shelves and external interface functions.
 GLI
 Interface Unit: provides GE optical interface and supports physical
backup. SD1–SD2, SD3–SD4, SD5–SD6 and SD7–SD8 are backup
groups.
 Processing Unit: implements bi-directional IP packet table look-up,
fragmenting, forwarding and traffic management.
 Queue Management Unit: implements bi-directional queue
management.
 The GE optical interface receives user plane data from the GUIM and
sends it through the backplane to the PSN board for user plane data
exchange.
SD1~SD8 (GE Optical)
Optical&Ethernet Queue Management

Back Board
Processing Unit
Interface Unit Unit

CP FE
Logic Unit CPU
PSN
 Provides bi-directional Inner bus
user plane data switch CP FE
CPU
with a capacity of 40
Gbps on each direction
 The data from each GLI

Back Board
LVDS
board is sent to the Matrix
Switching Unit through
the high-speed serial
links on the backplane. It
is switched and then sent Logic Unit
to the destination GLI
board.
Matrix Switch Unit
Peripheral Monitor Unit (PMU)
 Includes the PWRD board and the alarm box
 PWRD is responsible for collecting some
peripheral and environment board information
within the cabinet, including the power distributor
and fan status as well as some environment
alarms like temperature/humidity, smog, water and
infrared alarms. Each cabinet has one PWRD
board.
 The Alarm Box (ALB) can report system alarms at
different levels according to system fault grades to
facilitate timely interference and handling by
equipment management personnel.
Board Summary 1
Board Summary 2
Board Summary 3
Control Plane and User Plane Interconnection
BPSN BCTC
SBCX
PSN UIMC UIMC OMP HUB

GLI GLI CHUB CMP

BGSN BGSN
GUIM GUIM
UIMU( UIM_2) UIMU( UIM_2)
User Control User Control
Circuit Circuit
plane plane plane plane

DTB
GUP2 SPB2 GUP2 GIPI
SDTB2

E1 STM-1 IP

Abis/A /Gb iOMCR Client

Active/Standby Board Design
 Key boards have 1+1 backup.
 Key interface boards such as GIPI and SDTB can have 1+1
backup if necessary.
 GLI and PSN boards work in the load sharing mode.
BGSN BCTC
OMP/CMP OMP/CMP
GUIM (Main) (Standby) (Main)

Control Plane

CHUB UIMC
User Plane
CHUB UIMC

GUIM (Standby) BPSN

Control Plane UIMC

GLI/PSN

User Plane GLI/PSN UIMC

General Description of Boards

 Front board and rear board

 Rear boards are passive boards that provides cabling
from the backplane (such as E1 and network cables) in
order to work together with corresponding front boards.
 Front boards are physical boards that process
resources. All system optical cables are led from the
front board panels.
 All front boards have four indicators on their
panels (RUN, ENUM, ACT, ALM) to indicate board
status.
Indicators on Board Panels
Indicator Color Meaning Description

Running Flashing at 1 Hz: the board is running normally

RUN Green
indicator Flashing at 5 Hz: version downloading is in process.
Flashing at 5 Hz: version download fails; board self test
Alarm
ALM Red fails because of inconsistency between board and
indicator
configuration
Solid on: the microswitch is opened; the board is not in
position; or version files are not downloaded.
Flashing at 5 Hz (quickly): the microswitch generates an
Board alarm because it is opened when the board is still running.
ENUM Yellow extraction
indicator Flashing at 1 Hz (slowly): the board can be extracted. The
microswitch is opened when the board is running, and the
board is in standby mode or release the resource.
Solid off: the microswitch is normal.
Active/stan On: the board is active.
ACT Green dby status
indicator Off: the board is standby.
Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical
Units
 Signal Flow on iBSC Control Plane and User
Plane
 iBSC Internal Cable connection
iBSC Logical View
ZXG10 iBSC

CMPU

UPU
Access Switch
TC Unit
BTS Unit Unit

O& M Unit

MSC PMU

Pow er a nd Fa ns

SGSN
iBSC External Physical Interfaces
FE

E1
MSC/ MGW SGSN
STM -- 1

A Gb

DTB /SDTB2/GIPI SPB2/GIPI

iBSC

DTB /SDTB2/GIPI DTB /SDTB2 SBCX GIPI

Abis Ater

BTS iTC NetNumen OMCB MR

Access Unit–Abis Interface Unit (BIU)

 E1 Abis
 E1 borne TDM link
 IP Abis
 FE/GE borne IP link
 IPoE Abis
 E1 borne IP link
BIU - E1 Abis
The interface board can be the DTB or SDTB2 board. The access
capacity of SDTB2 is four times that of the DTB.

E 1 Abis
to TCU or UPU
BIPB2
BIU
User Plane

GUP2
Switching
1 Network
GUIM
DTB

2
T to CMP
32
SPB2

Control Plane Switching Network

LAPD2

Internal
E1/ T1 Ethernet HW
BIU - IP Abis
IP Abis
BIU
IPBB BIPB2

TCU

GUP2
GIPI

GUP2
UDP

User Plane
Switching
SCTP
Network

GUP2
to CMP UPU

Control Plane Switching Network

网

External Internal
Ethernet Ethernet HW
BIU - IPoE Abis
IPoE Abis

BIU
BIPB2
1 TCU
2

GUP2
DTB

EIPI
RTP RTP

GUP2
32
c UDP c UDP
ML/MC -PPP
PPP UDP
HDLC
User Plane
SCTP Switching
IP Network

GUP2
UDP

to CMP
UPU
Control Plane Switching Network

Internal
E1/T1 Ethernet HW
Access Unit- A Interface Unit (AIU)

 E1 A
 E1 borne TDM link
 IP A
 FE/GE borne IP link
AIU - E1 A
E 1A

AIU

1
TCU 2

DTB
User Plane 32

GUP2

GUIM
Switching
Network
1

SPB2
2

16
Control Plane Switching Network MTP2

Internal
E1/ T1 Ethernet HW STM -1
AIU - IP A
IP A

AIU
IPI AIPB

GUP2
GIPI

RTP RTP
UDP UDP

BIPB2

User Plane UDP

GUP2
Switching
SCTP Network

to CMP

Control Plane Switching Network

External Internal
Ethernet Ethernet HW
Access Unit–Gb Interface Unit (GIU)

 E1 Gb
 E1 borne TDM link
 IP Gb
 FE/GE borne IP link
GIU - E1 Gb
E 1 Gb

UPPB2 GIU

GUP2
1

SPB2
2

User Plane 16
Switching
UDP
Network 1

SPB2
2

16
Control Plane Switching Network

to CMP

Internal
E1/ T1 Ethernet
GIU - IP Gb
IP Gb

GIU
IPGB UPPB 2

GUP2
GIPI
UDP UDP

BIPB 2

User Plane UDP

GUP2
Switching
Network

to CMP
Control Plane Switching Network

External Internal
Ethernet Ethernet HW
O&M Unit

 OMP Board
 System operation and maintenance;
 Connects to the iOMCR;
 System management and monitoring
Switching Unit

OMPP
HH
OMP UU LMT -R
OMP
BB
SBCX
SVB

100 M Ethernet
Operation and Maintenance Networking
 The networking mode of SBCX is as follows: iBSC and
SBCX(OMP1) form a subnetwork, and
SBCX(OMC1)+NetNumen for a subnetwork. The local
OMM usually consists of the SBCX and the SBCX client
(LMT).Usually, LMT and the OMM client are installed on
the same PC. The PC is then put in a different equipment
room. The network interfaces of SBCX are connected to
the switches of each iBSC, and then connected to the
router. Then the cables are connected to the remote
NetNument using WAN connection.
 When the iBSC needs to manage SDR BTSs, the OMCB
server manages all SDR configurations (physical,
transmission and radio configurations), links, alarms and
versions. The OMCB program is installed on the SBCX
and a pair of GIPI boards must be configured.
Operation and Maintenance Networking
Processing Units & Monitoring Units

 Processing Unit - CMPU

 CMP Board
 PS/CS Service Call and Control Management
 BSSAP, BSSGP and System Resource Management
 Monitoring Unit - PMU
 PWRD board
 The PWRD board collects the environment monitoring
information of peripheral devices, including temperature
and humidity, smoke, water and infrared alarms.
UPU & TCU

 Processing Unit – UPU

 UPPB2: Processes PS protocols
 TransCoder Unit – TCU
 DRTB2: code transfer and rate adaptation
IP Switch Unit (PSU)
 Level 1 switch: GLI and PSN, 40G large-capacity user plane data switch.
 Level 2 switch: UIMU,GUIM, UIMC, and CHUB, responsible for the switch
and convergence of control plane and user plane data in the system.
Switch Control
st nd
1 Switch Subsystem 2 Switch Subsystem

2*GE FE

nd nd
2 Switch Subsystem 2 Switch Subsystem

GE
FE

BGSN 1 BGSN N
IP Switch Unit (PSU)
 If there are only two resource shelves, the Level-1 switch subsystem is
not needed on the user plane. The two resource shelves can be
directly interconnected using Gigabit optical interfaces.
Control
nd
2 Switch Subsystem

FE

nd nd
2 Switch Subsystem 2 Switch Subsystem
2*GE

GE
FE

BGSN 1 BGSN 2
Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
User Plane Signal Flow in the CS Domain

 The BIU severs user plane data from control plane

data, and then sends user plane data to the TCU,
which processes such data and then sends it to
the AIU. Signal flow 1→2.
UPU TCU

User plane A Interface

Abis Interface AIU
1 switch network
BIU

Gb Interface
Control plane GIU
switch network

CMP OMP
User Plane Signal Flow in the PS Domain
 The BIU severs CPU frames from all frames and sends them to the
UPU(UPPB2) through the user plane switching network. The UPU then
separates PS field user plane data from CPU frames received for
further processing. After data processing is complete, the data is sent
to the GUI through the user plane switching network.

UPU TCU

1 User plane 2 A Interface

Abis Interface Switching network AIU
BIU

Control plane Gb Interface

Switching network GIU

CMP OMP
Control Plane Signal Flow in the CS Domain
 Abis interface signal flow Abis interface unit (BIU) sends signaling in the
LAPD channel to the CMP board as control plane data. The CMP
processes such data and sends some of it directly back to the BIU (flow
direction: 1→1). Some signaling data will be sent to the AIU in the form of
A-interface signaling flow (flow direction: 1→2).
 A-interface signal flow: The AIU processes the MTP2 part of A-interface
signaling, and then sends it to the CMP to complete the processing of
MTP3 and layers above. Some global processes need the participation
of the OMP. The data flow direction is 2→3→3→2 or 2→2.
UPU TCU

User plane A Interface

Abis Interface Switching network AIU
2
BIU

Gb Interface
1 Control plane GIU
Switching network

CMP OMP
Control Plane Signal Flow in the PS Domain
 For some control plane signaling in the PS field, the system requests
resources from the CMP board, and then sends the signaling to the
UPPB2 for processing.
 When the MS is processing PS services, control plane signaling should
be separated from UPPB2 and then sent to the CMP for processing.

UPU TCU

User plane A Interface

2
Switching network AIU
Abis Interface
BIU
3
5 Gb Interface
1 Control plane GIU
Switching network

CMP OMP
Control Plane Signal Flow in the PS Domain
 Abis interface signaling flow
 The Abis interface unit (BIU) sends control plane data in
the LAPD channel to the CMP board. The CMP
processes such data and sends some of it directly back
to the BIU (flow direction: 1→1). Some data, such as
packet assignment messages, is sent to the UPU,
which processes the data and then sends it to the BIU
through the user plane switch network (flow direction:
1→3→2).
 Data from the Abis interface unit is sent to the UPU
through the user plane switch network. The UPU
processes the data and separates control signaling
packets, which are sent to the control plane processing
board (CMP).The data flow direction is: 2→3→3→2.
Control Plane Signal Flow in the PS Domain
 Gb interface signaling flow
 The GIU sends BVC channel data as control plane data to the
active CMP. The CMP processes the data and sends some of it
(such as PTP BVC restart) to other CMPs and some (such as
signaling BVC restart) to the OMP. The CMP or the OMP
processes the data and some signaling generates the Abis
signaling traffic, such as paging messages in the PS or CS field,
whose data flow is 5→1 or 5→3→2; other signaling, such as PTP
BVC restart acknowledgement and signaling BVC restart
acknowledgement, is sent to the Gb interface through the GUI, with
the data flow as 5→5 or 6→6.
 The GUI routes data from other BVC channels to the user plane
processing unit, which separates control plane data and sends it to
the CMP. The CMP processes the data and some signaling, such
as PTP paging messages, is sent to the Gb interface through the
GIU with the data flow as 4→3→5; some signaling generates the
Abis signaling flow, such as location messages, with the data flow
as 4→3→1.
User Plane Board Signal Flow in the CS Domain
 E1 Abis, E1 A

 The BIU severs user BPSN BCTC

SBCX
plane data from control PSN UIMC UIMC OMP HUB
plane data, and then
sends user plane data
to the TCU, which GLI GLI CHUB CMP

processes such data

and then sends it to the BGSN BGSN
AIU. GUIM GUIM
UIMU ( UIM _ 2 ) UIMU ( UIM _ 2 )
 Signal flow 1→2. UP CP Circuit UP CP Circuit

BIPB2 LAPD2 DTB DRTB2 SPB2 DTB

E1 Abis E1 A

A iOMCR Client
Control Plane Board Signal Flow in the CS Domain
 E1 Abis, E1 A

 The Abis interface unit BPSN BCTC

SBCX
(BIU) sends signaling in PSN UIMC UIMC OMP HUB
the LAPD channel to the
CMP board as control
plane data. The CMP GLI GLI CHUB CMP

processes such data

and sends some of it BGSN BGSN
generates the A GUIM GUIM
UIMU ( UIM _ 2 ) UIMU ( UIM _ 2 )
interface signaling flow UP CP Circuit UP CP Circuit
to the AIU.
 Signal flow 1→2.
BIPB2 LAPD2 DTB DRTB2 SPB2 DTB

E1 Abis E1 A

iOMCR Client
User Plane Board Signal Flow in the CS Domain
 IP Abis, IP A

BPSN BCTC
 The BIU severs user SBCX
plane data from control PSN UIMC UIMC OMP HUB
plane data, and then
sends user plane data
CMP
to the TCU, which GLI GLI CHUB

processes such data

and then sends it to the BGSN BGSN

AIU. GUIM
UIMU ( UIM _ 2 )
GUIM
UIMU ( UIM _ 2 )

 Signal flow 1→2. UP CP Circuit UP CP Circuit

BIPB2 IPBB AIPB IPI

IP Abis IP A

iOMCR Client
Control Plane Board Signal Flow in the CS Domain
 IP Abis, IP A

BPSN BCTC
 The Abis interface unit SBCX
(BIU) sends signaling in PSN UIMC UIMC OMP HUB
the LAPD channel to the
CMP board as control
plane data. The CMP GLI GLI CHUB CMP

processes such data

and sends some of it BGSN BGSN

generates the A GUIM

UIMU ( UIM _ 2 )
GUIM
UIMU ( UIM _ 2 )
interface signaling flow UP CP Circuit UP CP Circuit
to the AIU.
 Signal flow 1→2.
BIPB2 IPBB AIPB IPI

IP Abis IP A

iOMCR Client
User Plane Board Signal Flow in the PS Domain
 E1 Abis, E1 Gb

BPSN BCTC
 The BIU severs CPU SBCX
frames from all frames PSN UIMC UIMC OMP HUB
and sends them to the
UPU(UPPB) through the
user plane switching GLI GLI CHUB CMP

network. The UPU then

separates PS field user BGSN BGSN

plane data from CPU GUIM

UIMU ( UIM _ 2 )
GUIM
UIMU ( UIM _ 2 )
frames received for UP CP Circuit UP CP Circuit
further processing. After
data processing is
complete, the data is BIPB2 LAPD2 DTB UPPB2 GIPB2
sent to the GUI through
the user plane switching
E1 Abis E1 Gb
network.
 Signal flow 1→2. iOMCR Client
Control Plane Board Signal Flow in the PS Domain
 E1 Abis, E1 Gb

 The Abis interface unit BPSN BCTC

SBCX
(BIU) sends control PSN UIMC UIMC OMP HUB
plane data in the LAPD
channel to the CMP
board. The CMP GLI GLI CHUB CMP

processes such data

and sends some of it to BGSN BGSN
the UPU (such as GUIM GUIM
UIMU ( UIM _ 2 ) UIMU ( UIM _ 2 )
packet assignment UP CP Circuit UP CP Circuit
message). The UPU
processes such data
and then sends it to the LAPD2 DTB UPPB2 GIPB2
BIPB2
BIU through the user
plane switch network.
E1 Abis E1 Gb
 Signal flow 1→3→2.
iOMCR Client
Control Plane Board Signal Flow in the PS Domain
 E1 Abis，E1 Gb

 The GIU sends BVC BPSN BCTC

SBCX
channel data as control PSN UIMC UIMC OMP HUB
plane data to the main
CMP. The CMP
processes the data and GLI GLI CHUB CMP

some signaling
generates the Abis BGSN BGSN
signaling flow, such as GUIM GUIM
UIMU ( UIM _ 2 ) UIMU ( UIM _ 2 )
paging messages in the
UP CP Circuit UP CP Circuit
CS field
 Signal flow 5→3→2.
BIPB2 LAPD2 DTB UPPB2 GIPB2

E1 Abis E1 Gb

iOMCR Client
User Plane Board Signal Flow in the PS Domain
 IP Abis, IP Gb

 The BIU severs CPU BPSN BCTC

SBCX
frames from all frames PSN UIMC UIMC OMP HUB
and sends them to the
UPU(UPPB) through the
CHUB CMP
user plane switching GLI GLI

network. The UPU then

separates PS field user BGSN BGSN

plane data from CPU GUIM

UIMU ( UIM _ 2 )
GUIM
UIMU ( UIM _ 2 )
frames received for UP CP Circuit UP CP Circuit
further processing. After
data processing is
complete, the data is BIPB2 IPBB UPPB2 IPGB

sent to the GUI through

the user plane switching IP Abis IP Gb
network.
iOMCR Client
 Signal flow 1→2.
Control Plane Board Signal Flow in the PS Domain
 IP Abis, IP Gb
BPSN BCTC
 The Abis interface unit SBCX
(BIU) sends control PSN UIMC UIMC OMP HUB
plane data in the LAPD
channel to the CMP
CHUB CMP
board. The CMP GLI GLI

processes such data

and sends some of it to BGSN BGSN

the UPU (such as GUIM

UIMU ( UIM _ 2 )
GUIM
UIMU ( UIM _ 2 )
packet assignment UP CP Circuit UP CP Circuit

message). The UPU

processes such data
and then sends it to the BIPB2 IPBB UPPB2 IPGB

BIU through the user

plane switch network. IP Abis IP Gb

 Signal flow 1→3→2. iOMCR Client

Control Plane Board Signal Flow in the PS Domain
 IP Abis, IP Gb
BPSN BCTC
 The GIU sends BVC SBCX
channel data as control PSN UIMC UIMC OMP HUB
plane data to the main
CMP. The CMP
CHUB CMP
processes the data and GLI GLI

some signaling
generates the Abis BGSN BGSN

signaling flow, such as GUIM

UIMU ( UIM _ 2 )
GUIM
UIMU ( UIM _ 2 )
paging messages in the UP CP Circuit UP CP Circuit

PS or CS field
 Signal flow 5→3→2.
BIPB2 IPBB UPPB2 IPGB

IP Abis IP Gb

iOMCR Client
IP over E1 Signal Flow
 IPoE User Plane Signal Flow  IPoE Control Plane Signal Flow

BGSN BGSN

GUIM GUIM
UIMU ( UIM _ 2 ) UIMU ( UIM _ 2 )
UP CP Circuit UP CP Circuit

BIPB2 EUIP DTB BIPB2 EUIP DTB

IPoE Abis IPoE Abis

Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
System Interconnection Modes
 Most boards are managed by the OMP via the internal control plane.
 The ICM board are connected to the UIMC via the RS485 bus, and then
managed by the OMP.
 The PWRD board is directly managed by the OMP via the RS485 bus.

OMP OMC-R

P I S G D G S G C C G P U
W C P I T U D U M H L S I
R M B P B P T I P U I N M
D I B M B C

RS485 Ethernet
Internal Communications Management
BPSN BCTC in 1# Rack

UIMC OMP
485 Signal
GLI UIMC CHUB CLKG

PWRD
in Each
User
Control Rack
Plane GUIM
Ethernet Plane CLKG
Ethernet
BGSN1
User Plane Ethernet UIMC
GUIM

Circuit Switch
BGSN2 Shelf
System Clock Capture and Distribution Principles

 The CLK board is responsible for

supplying clock signals and
external synchronization
functions. BITS interface，Line 8K referenceGPS reference

 Clock level: Level 3 clock BCTC

 The board extracts clock ICM
reference via A Iu interface and
drives multiple channels of timing 8K reference 8K ，16M 8K ，16M
reference signals for use by each Differential signals Differential signals Differential signals
interface shelf after intra-board BGSN BPSN
synchronization.
 Level 2 forwarding of the UIM GUIM UIMC

board
 DTB, SDTB2 and SPB2 can be DTB EIPI GIPI GLI GLI
used to extract line reference
 The BPSN does not need a clock
reference
Intra-shelf Cable Connection
 Clock extraction and distribution cables;
 Control plane and Ethernet interconnection cables;
 User plane optical cable connection;
 Monitoring cable.
Clock Extraction and Distribution Cables
 The clock extraction cable
connects the 8KOUT Power distribution subrack
interface on the DTB rear Fan subrack
board to the 8KIN interface G
on the ICM. BGSN
U
I
M
 The ICM can also extract
U O I C
GPS signals as the clock BCTC I M C H
M U
reference. C P M
B

 The clock distribution cables G

U
connect the CLKOUT BGSN I
M
interface on the ICM rear
U
board to the CLKIN BPSN I
M
interfaces on UIM boards in C

each shelf.
Control Plane and Ethernet Interconnection Cables

 The FE interfaces of the

CHUB rear boards connect Power distribution subrack
to the FE interfaces of the Fan subrack
UIM boards in each shelf. G
U
BGSN
 Internal GE connection is I
M
used inside the BCTC. U C
O I
I H
BCTC M
M C
U
C P M B
G
U
BGSN I
M
U
I
BPSN M
C
User Plane Optical Cable Connection
 The optical interface on the
GUIM front panel in the Power distribution subrack
BGSN connects to the Fan subrack
optical interface on the PLI G
U
front panel. BGSN I
M
 Supports physical backup. U C
O I
I H
BCTC M C
M U
P M
C B
G
U
BGSN I
M
U
G
I
BPSN L
M
I
C
Monitoring Cables
 The cables between fans to PWRD Sensor
boards are usually 120 ohm
twisted-pair cables that are Cabinet-top fan
connected to the FANBOX
Power distribution subrack
interfaces to monitor fan running
status. Fan subrack
G
 The environment monitoring sensor BGSN
U
I
is connected to the SENSORS M
U C
interface on the PWRD board to I
O
M
I
C
H
BCTC M U
collect environment alarms. C
P M
B
Fan subrack
 The door access sensor is
G
connected to the DOOR interface U
BGSN I
on the PWRD board to monitor door M

access status. G
U
I
BPSN L
M
 The PWRD board reports I
C

monitoring information to the OMP Fan subrack

board via RS485 cables.