0 Голоса «за»0 Голоса «против»

Просмотров: 21591 стр.Summary on JFET

Jan 05, 2018

© © All Rights Reserved

PPT, PDF, TXT или читайте онлайн в Scribd

Summary on JFET

© All Rights Reserved

Просмотров: 215

Summary on JFET

© All Rights Reserved

- Electronics For Dummies
- Arduino Essentials
- Principles of Transistor Circuits
- Practical Electronics Handbook
- Diode, Transistor & Fet Circuits Manual: Newnes Circuits Manual Series
- Basic Electronics
- Basic Electronics: Book 2
- Electrical Machines & their Applications
- Power Electronics and Motor Drive Systems
- Automotive Electronic Diagnostics (Course 1)
- Introduction to Power Electronics
- Troubleshooting Analog Circuits: Edn Series for Design Engineers
- Circuit Design: Know It All
- Embedded Systems: World Class Designs
- Eletrônica Básica
- The Maplin Electronic Circuits Handbook
- Electrical Installation Technology
- Marine Electrical Practice: Marine Engineering Series
- Embedded Hardware: Know It All
- RF Circuit Design

Вы находитесь на странице: 1из 91

Introduction

• There are two main types of FETs:-

Junction field-effect transistor (JFET) and

Metal-oxide semiconductor field-effect transistor (MOSFET).

(1) FETs are unipolar devices, they operate with only one type

of charge carrier.

voltage-controlled device where voltage between two of

the terminals (gate and source) controls the current through the

device.

Introduction

• A major feature of FETs is that they have very high input

resistance.

• Since the input of the FETs has very high resistance, the

device draws negligible currents. As a result, little heat is

dissipated in the device.

FETs in the circuit and we want to limit the heat created from

each FET.

The Junction Field-Effect

Transistor (JFET)

JFET has two regions: a p-type material and an n-type material.

Note that the p-type material actually surrounds the n channel. The p-

type region is diffused in the n-type material to form a channel and it

is connected to the gate lead.

Wire leads are connected to each end of the n-channel

Three leads of JFET

In comparison to the BJT, the three leads

of a JFET:

• gate – similar to BJT’s base

• source – similar to BJT’s emitter

Symbol for JFET

As in BJT, the arrow always point to n-type. In the n-channel JFET,

the gate is p-type. Hence the arrow points to the channel which is n-

type.

The JFET always operates with the gate-to-source pn

junction in reverse biased.

voltage.

VDD provides a drain-to-source voltage, thus

supplying a current from the drain to the source.

VGG supplies a negative voltage to the gate and sets a

reverse-bias voltage between the gate and the

source.

Why reverse bias?

region is produced along this pn junction. The depletion

region formed spreads into the n-channel.

It acts like a resistance to current flow.

The size of the depletion region depends on the biasing

voltage VGG. The higher VGG is, the larger the depletion

region.

Increasing VGG cause the depletion region to grow. It spreads

further into the n channel and the width of the n channel becomes

thinner. This creates more resistance against current flow.

region. The n channel becomes thicker and hence, creates less

resistance to current flow.

JFET Characteristics and

Parameters

Case 1: Gate-to-source voltage is zero (VGS = 0).

To get VGS = 0, short the gate-to-source junction (set VGG = 0).

As we increase VDD, VDS increases

as well. The drain current ID also

increases with VDD. This produces the

drain characteristic curve (ID versus VDS).

Depletion region

form in the n-

channel near to the

drain side.

It is not large

enough to have any

significant effect.

As VDS increases, the reverse bias voltage from gate to drain (VGD)

increases and produces a depletion region large enough to offset the

increase in VDS.

The offset is enough to keep ID constant (between B and point C).

The region between points B and C is called the constant – current

region.

At point B, the drain-to-source (VDS) voltage is called the pinch-off

voltage (VP), the ID axis is labeled IDSS which stands for drain-to-

source current with gate shorted. Both values are specified in

data sheets.

Breakdown

• ID will remain constant until point C, where we reach

breakdown.

enter the breakdown region.

• This will damage the device, thus a JFET should never be

operated in the breakdown region.

Case 2: Gate – to – source voltage is nonzero

(VGS 0).

the gate.

curves.

Each curve is produced with

one value of VGS.

is made more negative.

• This occurs because the channel is narrowing. Also notice that

pinch – off occurs at different VP’s for different VGS values.

cutoff voltage, VGS(off).

Note that the value of VGS that sets ID to zero (i.e. widening the

depletion region to a point where the channel is completely

closed) is the most negative value VGS can take.

ID is controlled by VGS. This is why JFET is a voltage-controlled

device.

Relation between pinch-off voltage, VP, and

cutoff voltage, VGS(off)

(i) VP is the value of VDS when the drain current becomes

constant. It is always measured at VGS = 0,

(ii) When VGS is nonzero, pinch-off occurs for VDS values less

than VP.

in sign. Thus, knowing one, we have the other.

Data sheets will generally list only one of the two. For

example, if VGS(off) = −5 V, then VP = + 5 V.

Example

put the JFET below in the constant-current region

of operation. The cutoff voltage, VGS(off) = − 4 V

and the IDSS = 12 mA.

Solution

Since VGS(off) = – 4V, thus VP = 4V.

The minimum value of VDS for the JFET to enter the constant current

region is

VDS = VP = 4 V

In the constant current area with VGS = 0 V,

ID = IDSS = 12 mA

VR(D) = IDRD = (12 mA) (560 Ω) = 6.72 V

Using KVL around the drain circuit

VDD = VDS + VR(D) = 4 V + 6.72 V = 10.72 V

Thus, VDD must be 10.72 V for the device to enter the constant current area,

i.e. to make VDS = VP.

Example

A particular p-channel JFET has a

VGS(off) = +4 V. What is ID when VGS = + 6 V?

Solution

Recall a p-channel JFET requires a positive gate-to-

source voltage. The more positive VGS, the less the

drain current.

When VGS = 4 V, ID = 0 (cutoff).

Any further increase in VGS keeps the JFET in cut off,

so ID remains at 0.

JFET Transfer Characteristic

For an n-channel JFET, VGS(off) is negative. The relation between

VGS and ID is known as the transfer characteristic curve (taken from

the drain characteristic curve ):

equation for the JFET transfer

characteristic curve

• The equation for the JFET transfer characteristic curve is:

2

V

ID = IDSS 1

GS

V

GS(off)

• Thus, if IDSS and VGS(off) are known, ID can be determined for any

VGS.

Because of this, JFET is referred to as a square-law device.

Example

Determine the drain current for VGS = 0 V, −1 V and –4 V for a 2N5459

JFET. Refer to the data sheet below.

Solution

From the data sheet, we find that IDSS = 9 mA and VGS(off) =

−8 V (maximum).

ID = IDSS = 9mA

1

8V

For VGS = –4V :

ID = 2.25 mA

JFET Forward Transconductance, gm

The ID vs VGS curve is also known as a transconductance curve.

The slope of the curve is known as the JFET forward transconductance:

gm = ΔID / ΔVGS (S).

Usually, it is very small so that it is measured in S.

Data sheets normally show the value of gm at VGS = 0 V (gm0). This value is

enough to calculate it for all values of VGS:

V

gm = gm0 1 GS

VGS(off)

The gm0 value can be calculate from

I DSS

gm0 = 2

VGS(off)

Input Resistance

Since a JFET operates with the gate-to-source junction

reverse biased, the input resistance is very high.

This is one advantage of JFET over BJT. The input

resistance can be calculated from

RIN = |VGS / IGSS|

Example

Determine the input resistance of the 2N5457 JFET.

Solution

The specification sheet for the 2N5457 JFET lists a maximum

gate reverse current (IGSS) of − 1 nA under the following

conditions:

T = 25 C, VDS = 0 V, VGS = − 15 V

|VGS / IGSS| = 15 G.

JFET Biasing

Just like the BJTs, we need to establish the correct

dc gate-to-source voltage to get the desired value of

drain current.

(i) Self-biased

(ii) Voltage-divider biased

(1) In any JFET circuit, all the source current passes

through the device to the drain circuit, i.e., IS = ID.

(2)This is because there is no significant gate current

because of the high input resistance,

IG = 0.

Self – Bias

• The self-bias circuit replaces the gate supply (−VGG)

with a gate resistor RG and a source resistor RS.

potential at the gate be VG.

RG does not affect the biasing of JFET. It is required for the ac

operation of the JFET. When an ac signal enters the gate, it will

be grounded if there is no RG. The presence of RG provides a

resistance to the path of the ac signal to the ground so that most

of the ac signal will go to the gate of the JFET.

produce a potential at the source VS.

Circuit Analysis

• Since IG 0,

VG = IGRG = 0.

VS = ISRS = IDRS.

• Then

VGS = VG – VS = 0 – IDRS = – IDRS.

• Now,

VD = VDD – IDRD

• Since VS = IDRS, the drain-to-source voltage is

VDS = VD – VS

= VDD – ID(RD + RS)

Example

For the particular JFET in this circuit, the

internal parameter values such as gm,

VGS(off), and IDSS are such that a drain

current, ID, of approximately 5 mA is

produced.

not produce the same results when

connected in this circuit due to the

variations in parameter values.

Solution

VS = IDRS

= (5 mA) (220 Ω) = 1.1 V

VD = VDD – IDRD

= 15 V – (5 mA) (1.0 kΩ) = 10 V

Thus,

VDS = VD – VS

= 10 V – 1.1 V = 8.9 V

Since VG = 0 V,

VGS = VG – VS

= 0 V – 1.1 V = – 1.1 V

Setting the Q-point of a Self-

Biased JFET

The basic approach to establishing a JFET bias point is

to determine ID for a desired value of VGS or vice versa.

Then, calculate the required value of RS by using

RS = |VGS / ID|

ways:

1. Directly from the transfer characteristic curve or

2. From the transconductance equation ID = IDSS with the

values of IDSS and VGS(off) obtained from the JFET data

sheet.

Example

Determine the value of RS

(at VGS = −5 V) required to

self-bias an n-channel

JFET that has the transfer

characteristic curve shown.

Solution

From the graph, ID = 6.25 mA at VGS = -5 V.

Then

RS = |VGS / ID| = 5 V / 6.25 mA = 800 Ω

Example

Determine the value of RS required to self-bias a p-channel

JFET with IDSS = 25 mA and VGS(off) = 15 V. VGS is to be 5 V.

Solution

Use the square-law equation:

2

V

1 GS

ID = IDSS V

GS(off)

= 11.1 mA

Now determine RS:

RS = |VGS / ID|

= 5 V / 11.1 mA = 450 Ω

Midpoint Bias

It is desirable to bias a JFET near the midpoint of its transfer characteristic

I

curve where ID = DSS .

2

Under ac signal condition, it allows the maximum amount of drain current

swing between

I DSS IDSS and 0.

When ID = 2 , 2

I DSS VGS

= IDSS 1

2

VGS(off)

V

0.5 ½ = 1 GS

V

GS(off)

VGS(off)

VGS = 0.29VGS(off) =

3.4

From this VGS value, the required RS can be determined.

To set the drain voltage at midpoint i.e. , select a value of RD to produce the

desired voltage drop.

Choose RG arbitrarily large to prevent loading on the driving stage in a

Example V DD

Select resistor values for RD and RS for the circuit +12 V

below to set up an approximate midpoint bias. For this

particular JFET, the parameters are IDSS = 12 mA and

VGS(off) = −3 V. RD

Solution

For midpoint bias,

ID IDSS/2 = 6 mA

and

VGS VGS(off) / 3.4 = − 882 mV RG

RS

Then, 10 M

RS = |VGS/ID|

= 882 mV / 6 mA = 147 Ω

From

VD = VDD − IDRD,

RD = (12 V − 6 V) / 6 mA = 1 k

Graphical Analysis of a Self-Biased

JFET

• Find VGS at ID = 0,

VGS = −IDRS = (0)(470 Ω) = 0 V

ID = IDSS:

VGS = −IDRS

= −(10 mA)(470 Ω) = −4.7 V

• Draw a line (dc load line)

connecting the two

points. Wherever the

load line intersects the

characteristic curve,

we have the Q-point

of the circuit.

Voltage – Divider Bias

• The voltage at the source VS must be more

positive than the voltage at the gate VG in order to

keep the gate-to-source junction reverse biased.

• The source voltage is VS = ISRS. The voltage at

the gate is

R

V V 2

2

G DD

• Thus, R R1

VGS = VG − VS = VG − ISRS

ID = (VG − VGS) / RS

Example

• Determine ID and VGS for the JFET with voltage-

divider bias shown. For this particular JFET, the

internal parameters are such that VD 7 V.

Solution

ID = (VDD – VD)/RD

= (12 V – 7 V) / 3.3 kΩ = 1.52 mA

VS = IDRS

= (1.52 mA) (2.2 kΩ) = 3.34 V

VG = [R2/(R1 + R2)]VDD

= [(1 MΩ)/(7.8 MΩ)] 12 V = 1.54 V

VGS = VG – VS

= 1.54 V – 3.34 V = –1.8V

Graphical Analysis of a JFET with

Voltage-Divider Bias

• The approach is similar to that in self-bias. In this case,

however, when ID = 0, VGS is not zero because the voltage-

divider produces a voltage at the gate independent of the

drain current.

• For ID = 0,

VGS = VG

• The next point taken to determine the dc load line in at VGS

= 0,

VG

ID =

RS

Stability

The transfer characteristics of a JFET can differ considerably from

one device to another and this affects the Q-point stability.

circuit. This is because the slope of the dc load line in a voltage-

divider bias is much smaller.

Although VGS varies quite a bit for both self-bias and voltage-

divider bias, ID is much more stable with the voltage-divider bias.

range of Q-points is reduced.

Consider the n-channel JFET spec sheet :

characteristic curves

The Metal – Oxide Semiconductor

Field-Effect Transistor

(MOSFET)

• Main drawback to JFET operation - JFET gate-to-source

must be reverse-biased in order to control the effective

size of the channel.

• This type of operation is referred to as depletion-mode

operation.

enhancement mode and the depletion-mode

(1) Depletion (D) MOSFETs and

(2) Enhancement (E) MOSFETs.

• The construction of the MOSFET differs from the JFET in that it has

no pn junctions.

thin layer of silicon dioxide (SiO2). The gate terminal is made of a

metal conductor.

• Thus, going from gate to the channel, you have metal, oxide and

semiconductor layers, which is where the term MOSFET comes

from.

MOSFETs.

For the n-channel D-

MOSFET: the substrate is p-

type, the channel is n – type.

D-MOSFET

• The center line in the circle represents the channel. The arrow, as usual,

points toward the n-type.

• An n-channel MOSFET operates in the depletion mode (similar to that of

JFET) when a negative gate-to-source voltage is applied.

• When a positive gate-to-source voltage is applied, the n-channel MOSFET

operates in the enhancement- mode.

• The D-MOSFET can operate both in the enhancement and depletion

modes.

Depletion Mode

• Negative voltage to the gate:

negative charges on the gate repel

the conduction electrons from the

channel, leaving the positive ions in

their place.

• That decreases the conductivity of

the channel.

• The greater the negative voltage on

the gate, the greater the depletion of

n-channel electrons.

• At a sufficiently large gate-to-source

voltage VGS(off), the channel is

completely depleted and ID becomes

zero.

• Just like the n-channel JFET, the n-

channel D-MOSFET conducts drain

current for gate-to-source voltages

between VGS(off) and zero.

Enhancement Mode

• In the enhancement mode, a

positive gate voltage applied to

the D-MOSFET effectively

widens the channel and reduces

its resistance.

Enhancement MOSFET

An E-MOSFET does not actually

have a channel. It depends on the

gate voltage to form a channel

between the source and drain

terminals.

to the SiO2 layer.

operates only in the enhancement mode.

In other words, the gate-to-source

potential must always be positive.

n-channel E-MOSFET

• A positive gate voltage applied above a

threshold value VGS(th) induces a channel

by creating a thin layer of negative charges

in the substrate region adjacent to the SiO2

layer.

increased the gate-to-source voltage. This

pulls more electrons into the channel area.

VGS(th), there is no channel.

E-MOSFET

The dashed line indicates the absence of a channel.

MOSFET Characteristics and

Parameters

• Most of the characteristics of the JFET apply to

the MOSFET.

E.g. the transconductance equation for the D-

MOSFET is the same as that of the JFET.

and where ID = 0, it corresponds to VGS(off).

• There are some differences with the E-MOSFET which only operates under

the enhancement mode. It requires a positive gate-to-source voltage. (n-

channel)

• It does not have a significant IDSS parameter, as do the JFET and the D-

MOSFET.

• Ideally, there is no drain current until VGS reaches a certain non-zero value

called the threshold voltage VGS(th).

ID = 0 for 0 < VGS < VGS(th)

Equation for the drain current

• The square law equation for the drain current of the E-

MOSFET is:

V

2

IDK= V GS GS th

given by IDon

V th

K=

V

2

GS GS

at the specified value of ID called the on-state value, ID(on),

at the given value of VGS.

Data Sheet

Example

From the data sheet above, determine the drain current for

VGS = 5 V.

Solution

From the data sheet, ID(on) = 500 mA at VGS = 10 V and VGS(th)

= 1 V.

Solving for K:

I 500

mA

Don 2

K= mA/V

6

.

17

V

V

GS

GS

2

10

V

th1

V 2

Thus,

ID =

K VGSVGSth 2

= (6.17)(5 − 1) = 98.7 mA

2

Handling precautions!!

• The layer of SiO2 that insulates the gate from the channel is extremely thin and

can be easily destroyed by static electricity. Hence, extra precautions must be

made in handling MOSFETs.

• Since the gate of a MOSFET is insulated form the channel, the input resistance

is very high. The gate leakage current (IGSS) is in the pA range (compared to the

gate reverse current for a JFET which is in the nA range). An input capacitance

results from the insulated gate structure. Excess static charge can be

accumulated because of the combination of the input capacitance with the very

high input resistance (like a RC circuit). This can result in damaging the device.

1. MOS devices should be shipped and stored in conductive foam. Do not use

styrofoam because it is the best static electricity generator ever devised.

2. All instruments and metal benches used in assembly or testing should be

connected to earth ground (third prong on 110 V wall outlets).

3. Assembler’s or handler’s wrist must be connected to earth ground with a length

of wire and a high value series resistor,

4. Never remove a MOS device (or any other device, for that matter) from the

circuit while the power is on.

5. Do not apply signals to a MOS device while the dc power supply is off.

MOSFET Biasing

D-MOSFET Biasing

• Recall that D-MOSFET can be

operated with either positive or

negative values of VGS.

• A simple bias method is to set VGS =

0 so that an ac signal at the gate

varies the gate-to-source voltage

above and below this 0 V point.

• A D-MOSFET with zero bias is

shown in the figure below. Since VGS

= 0, ID = IDSS as indicated. The drain-

to-source voltage is expressed as

VDS = VDD − IDSSRD

Example

Determine the drain-to-source voltage given that VGS(off) = − 8

V and IDSS = 12 mA.

Solution

The drain-to-source voltage is

VDS = VDD − IDSSRD

VDS = 18 V − (12 mA)(620 )

= 10.6 V

E-MOSFET Biasing

• Several of the biasing circuits used for

JFETs and D-MOSFETs cannot be used

to bias E-MOSFETs because the

enhancement mode of operation

requires a positive value of VGS.

MOSFET are the voltage-divider bias

and drain-feedback.

E-MOSFET Biasing

Since VGS must be greater than the threshold value

VGS(th), the goal is to make the gate voltage more

positive than the source by an amount exceeding

VGS(th).

of collector-feedback bias for BJT.

• The drain-feedback bias circuit has a negligible gate

current.

• Thus, there is no drop across RG.

• Hence,

VGS = VDS.

E-MOSFET Biasing

R

V V 2

2

GS DD

R R1

VDS = VDD − IDRD

where ID= KV

V

GS GSth

2

.

Example

Determine VGS and VDS for the E-MOSFET circuit in figure below.

Assume this particular MOSFET has minimum values of ID(on) =

200 mA at VGS = 4 V and VGS(th) = 2 V.

Solution

K = ID(on)/(VGS–VGS(th))2 = 200 mA / (4V–2V)2

= 50 mA/V2

ID = K(VGS−VGS(th))2 = (50mA /V2)(3.13V–2V)2

= 63.8 mA

Finally, calculate VDS.

VDS = VDD – IDRD = 24 V – (63.8 mA) (200 Ω) = 11.2 V

FET Amplification

ID

The transconductance of a FET is defined as, gm

VGS

.

Id

In ac quantities, gm

Vgs

.

input voltage Vgs multiplied by the transconductance gm.

Small signal model

Id

Id G D

D

G

Vgs Vds

gmVgs rd

S

S

VDD

Example RD

IRD

Io

ID Vo

Ii D

G

Vi

S

RG

VGG

Ii Id Io

G D

IRD,ac

Vi RG gmVgs rd RD Vo

Zi

S Zo

Equivalent circuit that represents the relationship

Id = gmVgs.

assumed to be large enough so that

they are open circuits.

A FET simplified equivalent circuit with an external ac drain

resistance .

The ac voltage gain is

Vds

Av = .

V gs

Id

Since Vds = − IdRd, and Vgs= , thus

gm

Av = −gmRd

There are two cases that Av can change:

of the FET, the gain is affected. It becomes:

R

Av=− gm

1g R

d

m s

sufficiently greater than Rd (at least 10 times

greater), it appears in parallel to Rd, the gain is

reduced to the following: Rdrds '

Av=− gm

'

Rd rds

Common-Source Amplifiers

JFET Amplification

A common-source amplifier is one with no source resistor (as far as ac

signal is concerned), so the source is connected to the (ac) ground.

It is biased such that the input stays within the linear region of operation.

The ac input signal causes the gate-to-source voltage to swing above and

below its Q-point value (VGSQ).

As the drain current , VR(D) , VD .

The drain current is in phase with the gate-to-source voltage. The drain-to-

source voltage is 180o out of phase with the gate-to-source voltage.

DC Analysis

Develop a dc equivalent circuit by replacing

all capacitors with opens. Then we

determine ID. If the circuit is biased at

midpoint of the dc load line, then ID =

IDSS/2.

OR

Solve for ID using the equation

2

IDRS

ID = IDSS 1

V

GS

(off

)

AC Equivalent Circuit

Replace the capacitors by shorts and the dc sources by a ground.

AC Equivalent Circuit

Since the input resistance to a FET is very high, all of the input

voltage from the ac signal source appears at the gate with very

little voltage is dropped across the internal ac source

resistance:

Vgs = Vin

The gain is given by

Av =−gmRd.

Vout = Vds = AvVgs

= −gmRdVin

Example

What is the total output voltage at the unloaded amplifier

shown below? Assume IDSS = 770μA and VGS(off) = –3 V.

Solution

First find the dc output current. We need to solve the quadratic equation:

2

ID = IDSS IDRS

1

V

(off)

GS

Rewriting the initial equation:

R2

S I

2

2

RS 1

I1

0

2D

V D

V ) I

GS

( )

off GS

(

off DSS

R2 2RS 1

, and

S

Let A = 2,

B= C = 1.

VGS(off ) VGS

(off) IDSS

Then we get

AID2 + BID + 1 = 0

and the solution is

ID = (20.2 mA, 0.54 mA)

With this value for the drain current, determine the value of the drain

voltage:

VD = VDD – IDRD

= 12 V – (0.5mA) (3.3 kΩ)

= 10.2 V

VGS = − IDRS = − (0.5 mA) (910 Ω) = –0.46 V

I DSS

gm0 = 2

VGS(off)

= 2 (770 μA) / 3 V = 0.51 mS

V 1.78V

gm01 GS 0 .51mS

1

V =

gm =

GS )

(off 3V

= 432.7 μS

Finally, the ac output is

Vout = AvVin = −gmRDVin

= − (433 μS)(3.3 kΩ)(100 mV)

= − 143 mVrms

(143mV) (1.41) = 202 mV

peak value riding on a dc level of 5.53 V.

Input Resistance

resistance of the amplifier, we use the equation:

Rin = RG||(VGS/IGSS)

where IGSS is the leakage current.

D – MOSFET Amplification

A zero-biased common-source n-channel D-MOSFET with an

ac source is capacitively coupled to the gate shown.

terminal is at ground, thus making VGS = 0 V.

The signal voltage causes Vgs to swing above and below

its zero value, producing a swing in Id.

• The negative swing in Vgs produces the depletion mode and Ids

decreases. The positive swing in Vgs produces the enhancement

mode and Ids increases.

• Note the enhancement mode is on the right of the vertical axis and

the depletion mode is on the left.

The dc analysis of this amplifier is somewhat easier than for a

JFET because ID = IDSS at VGS = 0. Since ID is known, the analysis

involves calculating only VD.

VD = VDD − IDRD

Example

The D-MOSFET shown earlier has the following values: RD = 33 , RG

= 10 M, C1 = 10 F, C2 = 10 F, RL = 8.2 k, IDSS = 200 mA and a gm

= 200 mS.

Determine both the dc drain voltage and ac output voltage. Given Vin =

500 mV.

Solution

Since the amplifier is zero – biased,

ID = IDSS =200 mA

And, therefore,

VD = VDD − IDRD

= 15 V − (200)(33) = 8.4 V

Rd = RD||RL = 32.9

Vout = −gmRdVin = −3.29 V

E-MOSFET Amplification

• The circuit shows a common-source n-channel E-MOSFET with

voltage-divider bias with an ac source capacitively coupled to the gate.

The gate is biased so that VGS > VGS(th).

• The signal voltage produces a swing in Vgs above and below its Q-

point value VGSQ. This in turn causes a swing in Id above and below its

Q-point, IDQ.

• The general procedure is to solve for the VGS, then get ID,

and finally VDS. That is,

R

V V 2

2

GS DD

R R1

K from ID(on) and corresponding VGS

ID = K(VGS – VGS(th))2

Example

A common source amplifier using an E-MOSFET is shown below. Find VGS,

ID, VDS, and the ac output voltage. Assume that ID(on) = 200 mA at VGS = 4 V,

VGS(th) = 2 V, and gm = 23 mS. Vin = 25 mV.

Solution

R

V V 2

2

GS DD

R R1

= (8.2 kΩ) / (55.2 kΩ) 15 V = 2.23 V

For VGS = 4 V, we get:

IDon

K=

VGSV th

GS

2

Therefore,

ID = K(VGS – VGS(th))2 = (50 mA/V2)(2.23 V–2V)2 = 2.65 mA

VDS = VDD – IDRD = 15 V – (2.65 mA)(3.3 kΩ)

= 6.26 V

Rd = RD||RL = 3.3 kΩ||33 kΩ = 3 kΩ

Vout = AvVin = −gmRdVin = −(23 mS)(3 kΩ)(25 mV) = − 1.73 V

Common – Drain Amplifiers

The common-drain amplifier is similar to the common-

collector BJT amplifier in that the Vin is the same as Vout with no

phase shift.

The gain is actually slightly less than 1. Note the output is

taken from the source.

Common-Gate Amplifiers

The common-gate is similar to the common-base BJT amplifier in that it has a

low input resistance.

The voltage gain can be determined by the same formula as used with the

JFET common-source amplifier.

The input resistance can be determined by the formula below.

Rin(source) = 1/gm

- Laboratory Report JFET Transistor CharacteristicsЗагружено:bravo5charlie
- Discussion JfetЗагружено:Aldwin Alquitran
- MOSFET Turn on (Tutorial 01)Загружено:Muhd Azwan
- Information Theory-pptЗагружено:Suhas Ns
- FET-FinalЗагружено:Matthew Alexander
- 1.Introduction VLSIЗагружено:ArjunSahoo
- Section 15 - Digital CommunicationsЗагружено:Cherryl Almojuela
- 2. FET Biasing(1)Загружено:A.K.M.TOUHIDUR RAHMAN
- LpvЗагружено:Mahesh Babu Mahi
- Field Effect TransistorsЗагружено:Kimberly Bautista
- Electronic Circuit Design and AnalysisЗагружено:Blekmaan Francisco-Ntsalaka Benedictus-Dominus Obaskho-Mmemo
- JP-50-3-897.pdfЗагружено:Srikanth
- Semikonduktor 3Загружено:Muhamad Salim
- MOS TransistorЗагружено:veeyesyes08
- Lecture 6Загружено:kewancam
- Novel Technique in Charactarizing a Pv Module UsingЗагружено:International Journal of Research in Engineering and Technology
- EE305Загружено:api-3853441
- EWH08_5_6Загружено:vishwas_er2010
- metal oxide semiconductorЗагружено:kamal hameed tayy
- Mosfet Notes 2Загружено:Anil Sai
- Weset Band BanksЗагружено:Seid Takele Meresa
- lec34.pdfЗагружено:pankaj rangaree
- Mosfet as a SwitchЗагружено:Ashiq Hussain
- lecture10-140706.pdfЗагружено:Alexandre Kennedy
- 7374Загружено:Dan Esenther
- 7382Загружено:Dan Esenther
- 1NV04.pdfЗагружено:Olga Plohotnichenko
- irfp4321pbf.pdfЗагружено:Rivaldo Gomes
- Lab1Загружено:EliasA.Tiongkiao

- Intermediate Mathematics - Proof by InductionЗагружено:Enos Lolang
- 3703_202_2011 sem1.docxЗагружено:Rutendo Sedeya
- srrs4_2012a22Загружено:Alexandra Alx
- 261.pdfЗагружено:sidakan
- 97em MasterЗагружено:Joey Mclaughlin
- TAX Guide 2018 2019 for IndividualsЗагружено:Rutendo Sedeya
- Exponent_Rules_Practice.pdfЗагружено:Rutendo Sedeya
- BJT SummaryЗагружено:Rutendo Sedeya
- Capacitors & InductorsЗагружено:Rutendo Sedeya
- Test2 SolutionsЗагружено:Rutendo Sedeya
- SinusoidalProblemsNsolutions.pdfЗагружено:Rutendo Sedeya
- BMA101 Unit OutlineЗагружено:Rutendo Sedeya
- Phasors Experiment 18Загружено:Rutendo Sedeya
- ACpower.pdfЗагружено:nwnwasd
- AmplifierЗагружено:poojakhar
- Propositions by MaxiЗагружено:Rutendo Sedeya
- Automata TheoryЗагружено:Rutendo Sedeya

- Vehicle Replacement in the International Committee of the Red CrossЗагружено:kelazindagika
- Chap3Загружено:anon_257748454
- Tr-7 Calculation Nominal Weight Solid WallЗагружено:Jose Bustos
- Equacion de DiracЗагружено:batenas1
- PPAP ChecklistЗагружено:massfrompak
- Ip PythonЗагружено:Felipe Quezada Castañeda
- Ellipse DetectionЗагружено:Jenn Aoa
- Multilevel AnalysisЗагружено:Marisela Fuentes
- Questions JavaЗагружено:Vijay Saini
- Stata-12Загружено:shahadat
- Week 12 Tutorial 11 Review Questions and SolutionsЗагружено:Đặng Thịnh Nguyễn
- Logic GatesЗагружено:Rizwan Aboosalih
- Guidelines for Autmation testing.docxЗагружено:Gul Raiz Rana
- Aldo RossiЗагружено:Pavithra Sivasankaran
- HackenbushЗагружено:Orchid Majumder
- Introduction to Optimal Power Flow Models in Plex OsЗагружено:BertrandFocher
- Compiler Design AssignmentЗагружено:Abhimanyu Pandey
- Evolution_Of_South-Eastern_Mesoamerica_s.pdfЗагружено:Angel Sanchez Gamboa
- Guidance for Robustness/Ruggedness Tests in Method ValidationЗагружено:vg_vvg
- Lab 1Загружено:Nyree Robinson
- STAT844-444OutlineЗагружено:Jacob Freeman
- 15Загружено:Boonme Chinnaboon
- Swift 1971Загружено:EnriqueGD
- 8086 programingЗагружено:Sumant Arora
- 4.1A. Satoshi Nakamoto and People (1)Загружено:Eman
- ADA_QBЗагружено:sharma balwant
- Wing ResonanceЗагружено:Luke Anderson
- conf-procЗагружено:triogranger
- Impact of Transient Response of Instrument Transformers on Phasor MeasurementsЗагружено:nada213
- Using Propensity Scores to Help Design Observational Studies: Application to the Tobacco LitigationЗагружено:eifer4

## Гораздо больше, чем просто документы.

Откройте для себя все, что может предложить Scribd, включая книги и аудиокниги от крупных издательств.

Отменить можно в любой момент.