EE 319K

Introduction to Microcontrollers

Lecture 1: Introduction,
Embedded Systems, Product
Life-Cycle, ARM Programming

Erez, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 1-1

 Agenda
Course Description
Book, Labs, Equipment
Grading Criteria
Expectations/Responsibilities
Prerequisites
Embedded Systems
Microcontrollers
Product Life Cycle
Analysis, Design, Implementation, Testing
Flowcharts, Data-Flow and Call Graphs
ARM Architecture
Programming
Integrated Development Environment (IDE)

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 Useful Info
• No labs this week!
• Lab lectures start this Friday
• F 4–5, M 6:30–7:30 and 7:30-8:30 (ECJ 1.202)
• Office hours: see Canvas for most recent?
• TAs have office hours too
• They are not there to do your work for you
• One course == common exams and HW
• 2/23 7–8:30 (15%) 4/6 7–8:30 (20%) Final TBD (25%)
• Most of the learning is in the labs
• 10 labs 30% of grade
• HW is important too so 10% for motivation
• Read the book and lab manual!
• Canvas, Piazza, and
users.ece.utexas.edu/~valvano/Volume1/

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 Action Items

• Come introduce yourselves

• Take stock of resources
• Class Website (Volume1)
• Piazza for class discussions
• Email to reach TAs+Me
• E-Book: Search “Valvano e-book”
• Order board
• Install SW
• Read Chapters 1 & 2 of book

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 DOs and DON’Ts
DO DON’T
•Read •Don’t cheat!
• Book, lab, datasheets •Never look at
•Try before seeking help another student’s
•Follow Piazza/Canvas code (current or
previous)
•Discuss material with
others •Don’t let your partner
do all the work
•Homework (not labs) in
groups •Don’t copy software
from book or web
•Consult the web without attribution
•Track due dates •Don’t expect
handholding
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 EE306 Recap: Digital Logic
+3.3V
p-type source A ~A
A p-type n-type ~A
gate drain 74HC04
0 V active off +3.3V
+3.3V off active 0V A ~A A ~A
n-type drain
0 1
gate source
1 0

 AND, OR, NOT

 Flip flops
 Registers
Positive logic: Negative logic :
True is higher voltage True is lower voltage
False is lower voltage False is higher voltage

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1-7
 EE306, Also

• Problem solving
• Programming
• Debugging

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 EE302 Recap: Ohm’s Law
V=I*R Voltage = Current * Resistance
I=V/R Current = Voltage / Resistance
R=V/I Resistance = Voltage / Current

I = 3.7mA
I
Battery
V R V=3.7V R = 1k
Resistor

•P = V * I Power = Voltage * Current

•P = V2 / R Power = Voltage2 / Resistance 1 amp is 6.241×1018
•P = I2 * R Power = Current2 * Resistance electrons per second =
1 coulomb/sec
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 Medical
Embedded System
Automotive

 Embedded Systems are

Communications
Military
everywhere
 Ubiquitous, invisible
 Hidden (computer inside)
 Dedicated purpose
 Microprocessor
 Intel: 4004, ..8080,..
Comsumer Industrial

x86
 Freescale: 6800, ..
Embedded system 9S12,.. PowerPC
 ARM, DEC, SPARC, MIPS,
Microcontroller LM3S or TM4C Electrical,
mechanical,
PowerPC, Natl. Semi.,…
Processor chemical,  Microcontroller
or
 Processor+Memory+
I/O Ports
RAM optical
ROM
devices I/O Ports (Interfaces)
DAC Analog
Bus ADC signals

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 Microcontroller
 Processor – Instruction Set + memory + accelerators
 Ecosystem
 Memory
 Non-Volatile
o ROM
o EPROM, EEPROM, Flash
 Volatile
o RAM (DRAM, SRAM)
 Interfaces
 H/W: Ports
 S/W: Device Driver
 Parallel, Serial, Analog, Time
 I/O
 Memory-mapped vs. I/O-instructions (I/O-mapped)

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 Texas Instruments TM4C123
Cortex M4 Systick
System Bus Interface NVIC

GPIO Port A GPIO Port B

PA7
PA6
Eight Four
PB7
PB6 ARM Cortex-M4
PA5/SSI0Tx I2Cs PB5
PA4/SSI0Rx
PA3/SSI0Fss
UARTs PB4
PB3/I2C0SDA
+ 256K EEPROM
PA2/SSI0Clk PB2/I2C0SCL
PA1/U0Tx
PA0/U0Rx
Four
SSIs
CAN 2.0 PB1
PB0
+ 32K RAM
PC7 GPIO Port C GPIO Port D PD7 + JTAG
PC6 PD6
PC5
PC4
USB 2.0 Twelve
Timers
PD5
PD4
+ Ports
PC3/TDO/SWO PD3
PC2/TDI
PC1/TMS/SWDIO
JTAG Six
64-bit wide
PD2
PD1
+ SysTick
PC0/TCK/SWCLK PD0
+ ADC
PE5
GPIO Port E GPIO Port F
+ UART
PE4 ADC Two Analog PF4
PE3 2 channels Comparators PF3
PE2 12 inputs PF2
PE1 12 bits Two PWM PF1
PE0 Modules PF0

Advanced High Performance Bus Advanced Peripheral Bus

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 LaunchPad Switches and LEDs
R1 0
TM4C123 PF0
PF4
Serial PA1 R13 0 5V
PA0 Green
R29 Blue Red
+5 PB1
0 330 330 330
USB PD5
PD4 R12 SW1 SW2
R25 PF3
PB0 0
0
PD0 R11
R9 0
PB6 PF2
0
R10 0
PD1 R2 DTC114EET1G
PB7 PF1
0

 The switches on the LaunchPad

Negative logic
Require internal pull-up (set bits in PUR)
 The PF3-1 LEDs are positive logic
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I/O Ports and Control Registers
Read from port address
n n GPIO_PORTF_DATA_R
Processor
n n
DQ Input/Output Port

Write to port address

Direction bits
GPIO_PORTF_DIR_R
n 1 means output
DQ 0 means input
Bus Write to port direction register

The input/output direction of a bidirectional port

is specified by its direction register.
GPIO_PORTF_DIR_R , specify if
corresponding pin is input or output:
 0 means input
 1 means output

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 I/O Ports and Control Registers
Address 7 6 5 4 3 2 1 0 Name
400F.E608 - - GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGCGPIO_R
4002.53FC - - - DATA DATA DATA DATA DATA GPIO_PORTF_DATA_R
4002.5400 - - - DIR DIR DIR DIR DIR GPIO_PORTF_DIR_R
4002.5420 - - - SEL SEL SEL SEL SEL GPIO_PORTF_AFSEL_R
4002.551C - - - DEN DEN DEN DEN DEN GPIO_PORTF_DEN_R

• Initialization (executed once at beginning)

1. Turn on clock in SYSCTL_RCGCGPIO_R
2. Wait two bus cycles (two NOP instructions)
3. Unlock PF0 (PD7 also needs unlocking)
4. Set DIR to 1 for output or 0 for input
5. Clear AFSEL bits to 0 to select regular I/O
6. Set PUE bits to 1 to enable internal pull-up
7. Set DEN bits to 1 to enable data pins
• Input/output from pin
6. Read/write GPIO_PORTF_DATA_R 1-15
 Product Life Cycle
• Specifications
• Constraints
• Block diagrams
Analyze Design • Data flow graphs
Requirements
the
Constraints
problem
Development
New requirements
New constraints
• Hardware
Deployment Testing • Software
Done

Analysis (What?) Implementation(Real)

Requirements -> Hardware, Software
Specifications Testing (Works?)
Design (How?) Validation:Correctness
High-Level: Block Diagrams Performance: Efficiency
Engineering: Algorithms, Maintenance (Improve)
Data Structures, Interfacing

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 Data Flow Graph

Lab 8: Position Measurement System

Position Voltage Sample

0 to 2 cm 0 to +3.3V 0 to 4095
Sample
Position ADC ADC 0 to 4095
Sensor hardware driver
SysTick
ISR
SysTick
hardware Mailbox

LCD main
LCD
display driver Fixed-point
0 to 2.000

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 Call Flow Graph

Position Measurement System

main SysTick
ISR

SysTick ADC LCD

init driver driver

SysTick ADC LCD

hardware hardware hardware

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 Structured Programming
Common Constructs (as Flowcharts)
Sequence Conditional While-loop

Block 1

Block 1 Block 2 Block

Block 2

Parallel Distributed Interrupt-driven concurrent

Fork main Trigger
main1 main2 interrupt
Init1 Init2 Init

Join Body1 Body2 Body

Return from
interrupt

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 Flowchart
Toaster oven:

main Cook

Output heat
Input from is on
switch Too cold

Not pressed Input toast

Start temperature
Pressed
toast < desired
Cook toast  desired
Output heat
is off

return

Coding in assembly and/or high-level language (C)

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 Flowchart
 Example 1.3. Design a flowchart for a system that performs two independent
tasks. The first task is to output a 20 kHz square wave on PORTA in real time
(period is 50 ms). The second task is to read a value from PORTB, divide the
value by 4, add 12, and output the result on PORTD. This second task is repeated
over and over.

main A
void SysTick_Handler(void){
Clock PORTA = PORTA^0x01; E
Input n from B < } >
PORTB
PORTA = E void main(void){ A
PORTA^1 unsigned long n;
n = (n/4)+12 C while(1){
> n = PORTB; B
n = (n/4)+12; C
PORTD = n; D
Output n to }
PORTD D
}

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 ARM Cortex M4-based System
Microcontroller System bus
ARM® CortexTM-M
processor
Input
PPB ports
Internal
Advanced
peripherals High-perf Output
Bus ports
Instructions
Flash ROM Data
ICode bus DCode bus RAM

 ARM Cortex-M4 processor

 Harvard architecture
 Different busses for instructions and data

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 ARM Cortex M4-based System
 RISC machine
 Pipelining effectively provides single cycle operation for many instructions
 Thumb-2 configuration employs both 16 and 32 bit instructions
CISC
Many instructions
Instructions have varying lengths
Instructions execute in varying times
Many instructions can access memory
In one instruction, the processor can both
 read memory and
 write memory
Fewer and more specialized registers.
 some registers contain data,
 others contain addresses
Many different types of addressing modes
RISC
Few instructions
Instructions have fixed lengths
Instructions execute in 1 or 2 bus cycles
Few instructions can access memory
 Load from memory to a register
 Store from register to memory
No one instruction can both read and write
memory in the same instruction
Many identical general purpose registers
Limited number of addressing modes
 register,
 immediate, and
 indexed.
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 ARM ISA: Thumb2 Instruction Set

 Variable-length instructions
ARM instructions are a fixed
length of 32 bits
Thumb instructions are a fixed
length of 16 bits
Thumb-2 instructions can be
either 16-bit or 32-bit
 Thumb-2 gives approximately 26%
improvement in code density over
ARM
 Thumb-2 gives approximately 25%
improvement in performance over
Thumb

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 ARM ISA: Registers, Memory-map
R0 0x0000.0000
R1 256k Flash
R2 ROM 0x0003.FFFF
R3
R4 0x2000.0000
General R5 32k RAM
purpose R6 0x2000.7FFF
registers R7
R8 0x4000.0000
R9 I/O ports
R10
R11 0x400F.FFFF
R12
Stack pointer R13 (MSP) 0xE000.0000
Link register R14 (LR)
Internal I/O
Program counter R15 (PC) PPB 0xE004.1FFF

Condition Code Bits Indicates

N negative Result is negative TI TM4C123
Z zero Result is zero
V overflow Signed overflow Microcontroller
C carry Unsigned overflow
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 LC3 to ARM - Data Movement
LEA R0, Label ;R0 <- PC + Offset to Label
ADR R0,Label or LDR R0,=Label
LD R1,Label ; R1 <- M[PC + Offset]
LDR R0,=Label ; Two steps: (i) Get address into R0
LDRH R1,[R0] ; (ii) Get content of address [R0] into R1
LDR R1,R0,n ; R1 <- M[R0+n]
LDRH R1,[R0,#n]
LDI R1,Label ; R1 <- M[M[PC + Offset]]
; Three steps!!
ST R1,Label ; R1 -> M[PC + Offset]
LDR R0,=Label ; Two steps: (i)Get address into R0
STRH R1,[R0] ; (ii) Put R1 contents into address in R0
STR R1,R0,n ; R1 -> M[R0+n]
STRH R1,[R0,#n]
STI R1,Label ; R1 -> M[M[PC + Offset]]
; Three steps!!

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 LC3 to ARM – Arithmetic/Logic

ADD R1, R2, R3 ; R1 <- R2 + R3

ADD R1,R2,R3 ; 32-bit only
ADD R1,R2,#5 ; R1 <- R2 + 5
ADD R1,R2,#5 ; 32-bit only, Immediate is 12-bit
AND R1,R2,R3 ; R1 <- R2 & R3
AND R1, R2, R3 ; 32-bit only
AND R1,R2,#1 ; R1 <- Bit 0 of R2
AND R1, R2, #1 ; 32-bit only
NOT R1,R2 ; R1 -> ~(R2)
EOR R1,R2,#-1 ; -1 is 0xFFFFFFFF,
; so bit XOR with 1 gives complement

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 LC3 to ARM – Control
BR Target ; PC <- Address of Target
B Target
BRnzp Target ; PC <- Address of Target
B Target
BRn Target ; PC <- Address of Target if N=1
BMI Target ; Branch on Minus
BRz Target ; PC <- Address of Target if Z=1
BEQ Target
BRp Target ; PC <- Address of Target if P=1
No Equivalent
BRnp Target ; PC <- Address of Target if Z=0
BNE Target
BRzp Target ; PC <- Address of Target if N=0
BPL Target ; Branch on positive or zero (Plus)
BRnz Target ; PC <- Address of Target if P=0
No Equivalent
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LC3 to ARM – Subs,TRAP,Interrupt

JSR Sub ; PC <- Address of Sub, Return address in R7

BL Sub ; PC<-Address of Sub, Ret. Addr in R14 (Link Reg)
JSRR R4 ; PC <- R4, Return address in R7
BLX R4 ; PC <-R4, Return address in R14 (Link Reg)
RET ; PC <- R7 (Implicit JMP to address in R7)
BX LR ; PC <- R14 (Link Reg)
JMP R2 ; PC <- R2
BX R2 ; PC <- R14 (Link Reg)
TRAP x25 ; PC <- M[x0025], Return address in R7
SVC #0x25 ; Similar in concept but not implementation
RTI ; Pop PC and PSR from Supervisor Stack…
BX LR ; PC <- R14 (Link Reg) [same as RET]

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 ARM is a Load-Store machine

Code to set (to 1) bit 5 of memory address x400FE608

SYSCTL_RCGCGPIO_R EQU 0x400FE608

; EQU psedo-op allows use of
; symbolic name to represent a constant

LDR R1, =SYSCTL_RCGCGPIO_R ; R1 holds x400FE608

LDR R0, [R1] ; R0 holds contents of
; location x400FE608
ORR R0, R0, #0x20 ; bit5 of R0 is set to 1
STR R0, [R1] ; write R0 contents back to
; location x400FE608

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SW Development Environment
Editor KeilTM uVision®
Simulated Processor
Source code Start Microcontroller
Start
; direction register Debug
LDR R1,=GPIO_PORTD_DIR_R Session Memory
LDR R0,[R1]
ORR R0,R0,#0x0F
; make PD3-0 output I/O
STR R0, [R1]

Build Target (F7)

Object code Real Processor

0x00000142 4912
Microcontroller
0x00000144 6808
Download
0x00000146 F040000F Memory
0x0000014A 6008 Start
Debug
Session I/O
Address Data

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