TE 342

Digital Electronics for Engineers II

Lecture 00
Course Information and General Introduction

Semester II, 2014|2015

09 March 2015 ~ 19 June, 2015
19 March, 2015
 Course Information - 1/2

• Course
– TE 342
– Digital Electronics for Engineers II
– 4.0 Credit Units’ Core Course – 90 hours
• Hours
– 45 Lecture hours
– 15 Tutorial hours
– 30 Practical hours
– α Extra/less hours
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 Course Information - 2/2
 Students Expected  Regular Class Timings
• Good at: • Lectures
– Thursdays 0700~1000 hrs
– TE 242 (Prerequisite)
– Logical thinking • Tutorials
– TBD based on the groups

 Instructors
• Practicals
• Dr. Omar - 0652056136
– TBD based on the groups
• omarfh@gmail.com
• Mr. Chugulu -
• gchugulu@yahoo.ie  Office Hours @ CoICT
– Thursdays

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 Course Objectives

• To provide knowledge on: -

– designing,
– building and
– testing
• of digital electronic circuits

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 Course Outcomes
• 1. Be able to explain the operation of, analyze
and design of digital electronic circuits using
analytical method and simulation

• 2. Be able to construct, perform measurements

and evaluate digital circuits

• 3. Understand the function of digital test and

measurement equipment and be proficient at
using them.

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 Course Contents-1/2
Unit I Design of sequential logic circuits: state diagrams,
transition tables, state tables
Medium Scale Integrated (MSI) circuits: asynchronous &
Unit II synchronous counters, propagation delay, maximum clock
frequency, decade & binary counters, other counter MOD
number, down/up counters, presettable counters, cascaded
counters, counters applications, shift registers (PIPO, PISO,
SIPO, SISO), decoders, BCD-to-7-segment decoder/drivers,
encoders, multiplexer multiplexers applications, de-
multiplexers, magnitude comparators, tristate ICs and their
applications,
Integrated Circuit logic families: TTL series, ECL,
Unit III CMOS series, speed fanout, power requirements, noise
margin, data sheets, interfacing ICs from different logic
families.
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 Course Contents-2/2
Unit IV D/A & A/D conversion: D/A
converters, accuracy, resolution,
linearity error, full-scale range, full-
scale error , setting time, A/D
converters, sampling, resolution,
quantization, quantization error.
Unit V CAD of digital circuits and laboratory
experiments

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 Tentative Course Schedule-1/2
Wee Topics Rema
k rks
1~2 Course Information and General Introduction
3 Design of sequential logic circuits: state diagrams, Assignment
01

transition tables, state tables

4~5 Medium Scale Integrated (MSI) circuits:
asynchronous & synchronous counters, propagation Assignment
02
delay, maximum clock frequency, decade & binary
counters, other counter MOD number, down/up
counters, presettable counters, cascaded counters,
counters applications, shift registers (PIPO, PISO,
SIPO, SISO), decoders, BCD-to-7-segment
decoder/drivers, encoders, multiplexer multiplexers
applications, de-multiplexers, magnitude comparators,
tristate ICs and their applications,
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 Tentative Course Schedule-1/2
Week Topics Remarks
6~7 Integrated Circuit logic families: TTL series, ECL,
Assignment
CMOS series, speed fanout, power requirements, 03

noise margin, data sheets, interfacing ICs from

different logic families.
8 Mid-Term Test
9~10 D/A & A/D conversion: D/A converters, accuracy,
Term Project
resolution, linearity error, full-scale range, full-scale
error , setting time, A/D converters, sampling, Assignment
resolution, quantization, quantization error. 04

11~13 CAD of digital circuits and laboratory experiments

Assignment
05

14 Project Presentations/Demonstrations

15 Make-up/Revision/Summary/Wrap-up/Viva Voce

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 References/Text Books
1. John F. Wakerly, “Digital Design: Principles
and Practices”, 3rd Ed, 2000
2. Ronald J. Tocci, “Digital Systems:
Principles and Applications, “Prentice-Hall,
Recommended 5th Ed. 1991.
References and
Textbooks
3. Nigel P. Cook, “Introductory Digital
Electronics, “Prentice Hall, 1997.
4. Alan C. Dixon and James L. Antonakos,
“Practical Approach to Digital Electronics,
Prentice Hall, 1999.

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 Evaluation
• Assessment
– Pop-up Quizzes
• Unknown dates  Any time during class/tutorial/practical hours
– One Mid-term Test
– Assignments/Presentations
– Project/Demonstrations/Viva voce
– University Exam
• Strictly covering the whole syllabus

• Assessment
• CA - 40% of Final
– Pop-up Quizzes – 12.5% of CA
– Mid-Term Test - 50% of CA
– Assignments/Presentations - 12.5% of CA
– Projects/Demonstrations/Viva voce - 25% of CA
• UE - 60% of Final
Final = CA + UE
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