Folded Cascode OP Exercise

2012/11/02
 Design Procedure Kn=100uA/V2 Kp=40uA/V2

1. VCC=5~6V
2. Ibias=2uA
3. Gain > 60dB
4. Phase Margin > 60deg
5. ICMR=0V~3.75V
6. Vout=0.55V~4.4V
7. CL=2pF
8. GB=2.5MHz

Rout  [ gm9  ro9  ro11] || [ gm7  ro7  (ro5 // ro 2)]

Av  gm1  Rout  gm1  {[ gm9  ro9  ro11] || [ gm7  ro7  (ro5 // ro 2)]}

1
P1   (rad / s)
Rout  CL
 
 I 
Vin (max)  VCC V SG1, 2VSD3( SAT )  VSD31( SAT )  VCC  3
 | VTP1 |   VSD3( SAT )  VSD31( SAT )
 Kp(W ) 
 
 
1, 2
L

Vin(min) V DS 3, 4( SAT ) VTP1

 Design Procedure for P-Diff pair OTA Kp=40uA/V2
1. I3=3.6uA~8.4uA(Typ=6uA, +/-40% variation) SR(Typ)=6/CL=3V/us Kn=100uA/V2
, and choose I4=I5=0.5*6+6uA=9uA in balance condition
I4=I5=9uA*140%=12.6uA in worst condition
W W 2  I 4,5 25.2 W
) 4,5 
5.6
2  4
2. ( ) 4  ( )5    2.8 Set (
L 4
L L Kn(VDS 4,5( SAT ) ) 2 100(0.3) 2

3. Set I6=I7=6uA*140%=8.4uA in worst condition, But(1) KnM6,7 is affected by Vsb (2)

W W 2  8.4 16.8 W
) 6,7 
8.4
 2  14
( )6  ( )7    7.46 Set (
L L 2
Kn(VDS 6,7 ( SAT ) ) 100(0.15) 2 L 1.2
4. Set I8=I9=I10=I11=6uA*140%=8.4uA in worst condition
2  I 8, 9 W 10.5
W W 16.8 Set ( ) 8, 9   2  10.5
( )8  ( ) 9  2
 2
 10.5 L 2
L L Kp(VDS 8,9( SAT ) ) 40(0.2)
2  I10,11 W 10.5
W W 16.8 ( )10,11   2  10.5
( )10  ( )11    10.5 L 2
L L Kp(VDS10,11( SAT ) ) 2 40(0.2) 2
5. If GB=2.5MHz gm1  gm2  GB  CL  (2.5e  6)  2  (2e  12)  31.4(uA / V )
W W gm12 31.4 2 W W 3
( )1  ( ) 2    4.1 Set ( )1  ( ) 2   8  6
L L Kp  I 3 40  6 L L 4
W 2  I3 16.8
6. ( )3    10.5 Set (
W
)3 
10.5
 2  10.5
L Kp(VDS 3( SAT ) ) 2 40(0.2) 2 L 2
VCC 0 5V VINP=0~5.5
Ii1=6uA, 8.4uA, 3.6uA for TT, FF, SS
Test Bench for ICMR
 Simulation result in ICMR
TT
FF
SS

VO

TT
FF
SS

Iin

TT
FF
SS

Slope
VCC 0 5V VINP=-0.2~2.7
Ii1=6uA, 8.4uA, 3.6uA for TT, FF, SS Test Bench for Output Swing
 Simulation result in output swing (All MOS in SAT)
TT
FF
SS

VO

Slope
VCC 0 5V Test Bench for SR
VINP pwl 0 0, 20u 0, 20.01u 2, 30u 2, 30.01u 3 60u 3, 60.01u 2
Ii1=6uA, 8.4uA, 3.6uA for TT, FF, SS
 Simulation result in SR+

TT
FF
SS

VO

TT 2.64V/us
FF 3.72V/us
SS 1.57V/us
Slope
 Simulation result in SR-

TT
FF
SS

VO

TT 2.75V/us
FF 3.86V/us
SS 1.64V/us
Slope
VCC 0 5V VINP=0.55V, 2.15V, 3.75V
Ii1=6uA, 8.4uA, 3.6uA for TT, FF, SS
Test Bench for gain and phase margin
TT : Close Loop Gain=78.2dB Simulation result in closed loop simulation (VINP=2.15V)
phase margin =87.4o

P1=315Hz

GB=2.54MHz