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USING THE M68HC11 MICROCONTROLLER

by John Skroder
Introduction
What is a microcontroller and how is it different
from a microprocessor?
A microcontroller is actually a microcomputer on a
single piece of silicon. It incorporates a
microprocessor as a key element.

What are the elements and concepts of


microcomputer operation?
The M68HC11 microcontroller comes in many
versions and designed to meet various
requirements.
• Does the user need a RAM or ROM A to D?
• Does the user require lowest cost?
• Is the application simple?
There is an M68HC11 version to satisfy each
user’s requirements.
The Motorola uses the following nomenclature to identify its
M68HC11 microcontrollers:
MC 68HC x 11 xx

MC  indicates that the microcontroller is filly tested and


qualified.
68HC  it uses high speed, high density CMOS
technology.
X  a single digit number either 7 or 8. A 7 indicates that
on board program memory is EPROM. An 8 indicates
that this memory is EEPROM. Absent either no.,
Motorola supplies a general purpose operating system
called BUFFALO
11  the device is a part of the M68HC11 family.
xx  indicates the specific M68HC11 version. For
example A1 has 256 bytes of onchip RAM, 512
bytes of on chip EEPROM and no ROM or
EPROM.
the E9 has 512 bytes of onchip RAM, 512 bytes
of on chip EEPROM and 12K bytes of on chip
ROM.
Each M68HC11 version incorporates M6801
processor architecture in its CPU.
M68HC11 on chip devices:
The M68HC11E9 includes the following on chip
devices:
• 512 bytes of RAM
• 12K bytes of ROM. The BUFFALO ROM
operating system is stored in the ROM.
• 512 bytes of EEPROM
• Two bidirectional parallel ports. (PORTC and
PORTD)
• One input-only port (PORTE).
• One output only port (PORTB)
• One port (PORTA) includes individual input-only
(3), output-only (3) and i/o lines (2)
• A full duplex UART called Serial Communication
Interface (SCI).
• A synchronous serial interface called
Synchronous Peripheral Interface (SPI)
• An 8 bit ADC
• A pulse accumulator which counts voltage
transitions applied to PORTA pins by an
external device
• A 16 bit timer
M68HC11 CPU:
Instruction
handling
I
Instruction
Decoding/
sequencing
Address Handling
Control Bus D register
Signal/
ACCA ACCB F
Enables Stack Pointer(SP)
E
G X Index Register
ALU
D
Y Index Register
S|X|H|I|N|Z|V|C H
Condition Code
Program counter (PC) B
Register (CCR)
Address Latch A
Data Hnadling

Internal C
Data Bus Internal
Address
Bus
M68HC11 ADDRESSING MODES

Inherent Addressing Mode:


Never address memory locations.
A no. of inherent mode instructions use no operand. Some use an
implied constant such as 0 or 1. And some manipulate CPU
register data. The M68HC11 uses about 73 inherent mode
instructions.
Eg: INX, INY, WAI

Immediate Addressing Mode :


It uses constant value operands and includes these values in the
instructions itself. The immediate operands are indicated with a #
sign. 29, M68HC11 instructions can use immediate mode addressing.
Eg: LDX #1, LDAA #6

Extended Addressing Mode:


These instructions address operands that reside at memory
addresses. Consider STAA C06A instruction. This causes the CPU to
copy the content of ACCA into the memory location $C06A.
The assembler compiles this instruction into 3 byte instruction:
the first byte is the opcode, 2nd and 3rd bytes specify the data
transfers destination address

Consider LDX 10B. This instruction loads X register with


contents of address $010B(MS byte) and $010C (LS byte)

Thus an extended mode instruction incorporates the operand’s


full 2 byte address. 49 instructions can use extended mode.

Direct Addressing Mode:


Direct mode Addresses reside on memory page 0, i.e; these
address’ MS bytes are always $00 and so this can be eliminated
from the instruction. 40 instructions use this mode.
Eg: ADDA 0. This instruction causes the CPU to add the
contents of location $0000 to the contents of ACCA, and return
the sum to ACCA
Indexed Addressing Mode:
The CPU forms an indexed mode effective address by adding an
unsigned program byte to the contents of one of the index registers.
The program byte is called the indexed mode offset,
Eg: STAA D,X This instruction causes the CPU to add 8 bit offset $0D
to the contents of X register and then copy the contents of ACCA to
this effective address

Indexed mode instructions using the Y index register require an


opcode prebyte($18) to differentiate them from X indexed instructions.
53 instructions can use indexed mode addressing.

Relative Addressing Mode:


These instructions control program flow. A relative mode instruction
alters program flow by sign extending a 1 byte offset, called the
relative address then adding the sign extended 2 byte value to the
PC’s contents. In the case of a conditional branching the CPU adds
the relative address if the condition is true.
M68HC11 INSTRUCTIONS

Data and Address Handling Instructions:

LDAA – load accumulator A


LDAB - load accumulator B
LDD - load D register
LDX – load X register
LDY – load Y register
LDS load stack pointer
Each can load values using immediate, direct, extended or indexed
addressing modes

STAA – store accumulator A


STAB - store accumulator B
STD – store D register
STX - store X register
STY - store Y register
STS - store stack pointer
Each can use direct, extended or indexed addressing modes

TAB – transfers the contents of ACCA to ACCB


TBA - transfers the contents of ACCB to ACCA
TSX - transfers the contents of stack pointer+1 to X register
TSY - transfers the contents of stack pointer+1 to Y register
TXS - transfers the contents of X register-1 to the stack pointer
TYS - transfers the contents of Y register-1 to the stack pointer
To compensate for the SP increment by TSX and TSY , the TXS and
TYS instructions decrement the content of X or Y register before
transferring its contents to the SP
A transfer instruction’s destination is always another CPU register.
Therefore all transfer instructions use inherent addressing mode.

XGDX – exchange X and D register contents


XGDY - exchange Y and D register contents
These use inherent addressing mode.

Push and Pull Instructions:


Push and Pull instructions transfer the contents of ACCA, ACCB
and the index registers to and from the stack.

A programmer can establish a stack by taking two actions: First,


allocate a block of user RAM as a stack. Second, insert an LDS
instruction in the program. This LDS instruction must load the stack
pointer with the highest address of the allocated RAM block.
PSHA – Transfer the content of ACCA to the address pointed at by
stack pointer ; then decrement the stack pointer, (ACCA  M(SP);
Sp-1 SP)
PSHB - Transfer the content of ACCB to the address pointed at by
stack pointer ; then decrement the stack pointer, (ACCB  M(SP);
Sp-1 SP)
PSHX - Transfer the content of X register’s LS byte to the address
pointed at by SP. Decrement SP, Then transfer the content of X
register’s MS byte to the address pointed at by SP. Decrement SP
again.( X(LS)M(SP),SP-1SP, X(MS)M(SP),SP-1SP ).

PSHY - Transfer the content of Y register’s LS byte to the address


pointed at by SP. Decrement SP, Then transfer the content of Y
register’s MS byte to the address pointed at by SP. Decrement SP
again.( Y(LS)M(SP),SP-1SP, Y(MS)M(SP),SP-1SP ).
Pull instructions take just the opposite actions

PULA – Increment the SP, Transfer the content of the address


pointed at by SP to ACCA (Sp+1 SP, M(SP)  ACCA)

PULB - Increment the SP, Transfer the content of the address


pointed at by SP to ACCB (Sp+1 SP, M(SP)  ACCB)

PULX - Increment the SP, Transfer the content of the address


pointed at by SP to the X register’s MS byte. Increment the SP again.
Transfer the content of the address pointed at by SP to the X
register’s LS byte (Sp+1 SP, M(SP)  X(MS), Sp+1 SP,
M(SP)  X(LS))
PULY - Increment the SP, Transfer the content of the address
pointed at by SP to the Y register’s MS byte. Increment the SP
again. Transfer the content of the address pointed at by SP to the Y
register’s LS byte (Sp+1 SP, M(SP)  Y(MS), Sp+1 SP,
M(SP)  Y(LS))

These instructions use inherent mode addressing

Clear, Increment, decrement, Bit Set and Bit Clear Instructions:

Clear:
CLR – write $00 to a memory location
CLRA – change ACCA’s contents to $00
CLRB - change ACCB’s contents to $00

The CLRA and CLRB instructions use inherent addressing modes


only
CLR uses extended or indexed mode
Eg: CLR A – Clears the memory location $000A

Decrement instructions start with the letters DE:


Memory (DEC)
ACCA (DECA)
ACCB (DECB)
X register (DEX)
Y register (DEY)
SP (DES)

A decrement instruction causes the CPU to subtract one from the


contents of a specified CPU register or memory location

The DEC instruction uses extended or indexed mode. Other


decrement instructions use inherent mode.
Increment instructions add 1 to a register or a memory location.
These instructions start with IN. These are similar to decrement
instructions.

INC – add 1 to the contents of a memory location


INCA – add 1 to ACCA’s contents
INCB - add 1 to ACCB’s contents
INX - add 1 to X register’s contents
INY - add 1 to Y register’s contents
INS - add 1 to SP’s contents

BCLR(Bit Clear) & BSET(Bit Set) instructions are used to clear or set
selected bits in a memory location. A mask byte is provided with
these instructions. The mask byte specifies which individual bits to
set or clear. For example to clear 0, 2, 4,and 6th bits of a memory
location the mask byte will be $55(%01010101). Similarly 1’s in the
BSET mask byte specify memory bits to be set.
BSET and BCLR instructions use direct or indexed mode
Eg: assume X = $0100
Address 010C contains $ CC
To change the contents of location $010C to $44, we use
BCLR C,X,$88
Shift, Rotate and Logic Instructions:

• Shift and rotate instructions manipulate the contents of memory


locations or an accumulator.

• Arithmetic shift left instructions start with ASL and logical shift left
instructions start with LSL. These instructions shift target’s MS bit
into the C flag.
• ASL/LSL – shift a memory byte left – indexed or extended mode
• ASLA/LSLA – shift ACCA left. – inherent mode
• ASLB/LSLB -- shift ACCB left. – inherent mode
• ASLD/LSLD -- shift the D register left. – inherent mode

• All these instructions shift a zero into the target memory/register’s


LS bit
• All these shift a zero into target memory/register byte’s LS bit
• ASR – arithmetically shift a memory byte right – indexed or extended
• ASRA -- arithmetically shift ACCA right -- inherent
• ASRB -- arithmetically shift ACCB right -- inherent
All these instructions retain the sign bit and start with ASR

• LSR – logic shift a memory byte left -- indexed or extended


• LSRA -- logic shift ACCA right -- inherent
• LSRB -- logic shift ACCB right -- inherent
• LSRD -- logic shift the D register right -- inherent
• All these instructions shift a zero into the target memory/register’s MS
byte

• Both arithmetic and logic shift right instructions shift the target’s LS bit
into the C flag
• ROLA – rotate ACCA bits left
• RORA -- rotate ACCA bits right
• ROLB – rotate ACCB bits left
• RORB – rotate ACCB bits left
All these inherent mode
• ROL – rotate memory left
• ROR – rotate memory right
These two indexed or extended

• A rotate right instruction shifts target’s LS bit into the C flag and the
C flag into the target’s MS bit and bits 7 through 1 one place right

• A rotate left instruction shifts target’s MS bit into the C flag and the C
flag into the target’s LS bit and bits 7 through 1 one place left
• Two types in logic instructions

1. Instructions that find 1’s and 2’s complement of a memory location or


accumulator
2. Instructions that AND, OR, or XOR the content of an accumulator
with a memory byte

• Complement instructions (COM) invert all bit in an accumulator or


memory byte
• COM – extended or indexed
• COMA -- inherent
• COMB – inherent

• A NEG instruction 2’s complements the contents of an accumulator


or memory byte.
• NEG – extended or indexed
• NEGA -- inherent
• NEGB -- inherent
• ORAA – OR ACCA with memory
• ORAB – OR ACCB with memory
Eg: ORAB C005
• Immediate,direct,indexed or extended mode

• ANDA – AND ACCA with memory


• ANDB – AND ACCB with memory
Eg: ANDB C005
• Immediate,direct,indexed or extended mode

• EORA – exclusive OR ACCA with memory


• EORB – exclusive OR ACCB with memory
Eg: EORB C005
• Immediate,direct,indexed or extended mode
Arithmetic Instructions

Add instructions:
• ABA – add the contents of ACCA to the contents of ACCB. Return 8
bit sum to ACCA. -- Inherent mode
• ADDA – ACCA  ACCA + Memory. -- Immediate,direct,indexed or
extended mode
• ADDB – ACCB  ACCB + Memory. -- Immediate,direct,indexed or
extended mode
• ADDD – ACCD  ACCD + Memory. -- Immediate,direct,indexed or
extended mode, Add the conents of 2 memory locations (2 bytes) to
D register and return the result to D register.
• Eg: ADDD 3 – adds the contents of $0004 to the D register’s LS
byte and adds with carry the contents of $003 to the D register’s MS
byte and then returns the sum to the D register
• ADCA – ACCA  C + ACCA + Memory -- Immediate,direct,indexed
or extended mode
• ADCB -- ACCB  C + ACCB + Memory -- Immediate,direct,indexed
or extended mode

Subtraction instructions:

• SBA – subtract the contents of ACCB from the contents of ACCA.


Return 8 bit difference to ACCA. Update the C flag -- Inherent mode
• SUBA – ACCA  ACCA - Memory. Update the C flag --
Immediate,direct,indexed or extended mode
• SUBB – ACCB  ACCB - Memory. Update the C flag --
Immediate,direct,indexed or extended mode
• SUBD – ACCD  ACCD - Memory. -- Immediate,direct,indexed or
extended mode, Subtract the contents of 2 memory locations (2
bytes) from D register and return the result to D register. Update the
C flag
• SBCA – ACCA  ACCA - Memory - C. Update the C flag. --
Immediate,direct,indexed or extended mode
• SBCB -- ACCB  ACCB - Memory – C. Update the C flag. --
Immediate,direct,indexed or extended mode

Multiply instructions:
• MUL – multiplies the contents of two accumulators and returns the
product to the D register. Uses inherent mode.

Division instructions:
• IDIV – integer divide.
• FDIV – fractional divide.
Both of these divide the D register by X register and return 16 bit quotient
to the X register and 16 bit reminder to the D register. Use inherent
mode.
Difference between IDIV and FDIV:
• IDIV is used to divide whole integers. FDIV is used to carry the
quotient to the right of radix point.
• Eg: $nnnn/$dddd=$qqqq.f(h)f(h)f(h)f(h)f(l)f(l)f(l)f(l)
Where $nnnn = a 16 bit numerator
$dddd = a 16 bit dinominator
$qqqq = the 16 bit integer quotient
f(h)f(h)f(h)f(h)f(l)f(l)f(l)f(l) = the 32 bit fractional quotient
Use IDIV and FDIV to solve the problem as follows:

• Load the D register with $nnnn and X register with $dddd


• Execute IDIV. IDIV returns $qqqq to the X register and reminder to
the D register. Store the X register’s content as $qqqq. Leave the
reminder in the D register.
• Re-load the X register with $dddd
• Execute FDIV. This instruction divides smaller reminder by the larger
$dddd returns the fractional f(h)f(h)f(h)f(h) to the X register
And a new reminder to the D register. Store the X register’s contents as
f(h)f(h)f(h)f(h). Leave the reminder in the D register.
• Reload the x register with $dddd
• Execute another FDIV. Store the X register’s contents as f(l)f(l)f(l)f(l)

• DAA(decimal adjust accumulator) adjusts the sum of two packed


BCD bytes. Inherent mode. Use DAA after ABA, ADDA, or ADCA.
Condition Code Instructions:

• 8 M68HC11 instructions manipulates bits in the CCR. All use inherent


addressing mode.
• TPA – transfer the contents of CCR to ACCA
• TAP -- transfer the contents of ACCA to CCR
M68HC11 has no special instructions to set/reset the S and X bits. So
to manipulate these bits TAP and TPA are used. S and X bits can be
changed without disturbing the other CCR bits as follows:
First use TPA to transfer CCR’s contents to ACCA
Second OR/AND ACCA’s contents with mask: %bb000000, the two b’s
represents the desired S and X states.
Third use TAP to transfer the contents of ACCA back to CCR
Once a TAP clears the X bit, this bit cannot be set again even by another
TAP execution. Only an M68HC11 chip reset can set the X bit.
• 6 CCR oriented instructions simply set or reset the C, I, and V bits.
• SEC – set the C flag
• CLC – clear the C flag
• SEI -- set the I mask
• CLI -- clear the I mask
• SEV -- set the V flag
• CLV -- clear the V flag

Test and Compare instructions:

The M68HC11 can test the contents of ACCA or ACCB and set or reset
the CCR’s N and Z flags accordingly.
• TSTA – test ACCA’s contents to zero or minus
• TSTB -- test ACCB’s contents to zero or minus
These instructions use inherent mode. A TSTA or TSTB instruction
automatically subtracts zero from the contents of the subject
accumulator, then sets or resets the N and Z flag accordingly.
These instructions leave the target accumulator unchanged.
Z flag is set if accumulator contains $00.
N flag is set if the 7th bit of the accumulator is set

C and V flags are automatically set to zero.


S, X, H and I bits are unchanged.

• BITA – AND the contents of ACCA with the contents of memory byte.
Set or reset the N and Z flags accordingly. ACCA and memory byte
are unaffected.
• BITB -- AND the contents of ACCB with the contents of memory byte.
Set or reset the N and Z flags accordingly. ACCB and memory byte
are unaffected.
• for example to test bit 4 of ACCA BITA #$10 can be used. $10 is
mask byte
• BITA and BITB can access a memory location using immediate, direct,
extended or indexed modes ACCA can be loaded with the mask and
then accessing the memory byte to be tested using immediate, direct,
extended or indexed mode. Suppose the bits 3 and 7 of memory
location $C01Ahas to be tested, then
LDAB #88
BITB C01A
The BITB instruction ands the contents of ACCB and address $C01A
and then updates N and Z accordingly.
• BITA and BITB instructions automatically resets the V flag. The other
flag bits are unchanged.

• Five of the six compare instructions use comparison values residing in


memory. These instructions use immediate, direct, extended or
indexed modes to access the comparison values. These instructions
are
• CMPA – compares the contents of ACCA with a byte in memory
• CMPB -- compares the contents of ACCB with a byte in memory
• CPD -- compares the contents of D register with a 2 byte value in
memory
• CPX -- compares the contents of X register with a 2 byte value in
memory
• CPY -- compares the contents of Y register with a 2 byte value in
memory

• The sixth compare instruction uses inherent addressing mode. CBA


compares the contents of ACCA with ACCB and sets or resets the N,
Z, V, and C flags accordingly.
Program Control Instructions:

• These instructions alter the PC’s contents. There are 4 categories.


1. Unconditional branching
2. Conditional branching
3. Program jump instructions
4. Return instructions
• Unconditional branching:
1. BRA – branch always
2. BSR – branch to subroutine
• To execute BRA the CPU sign extends the accompanying relative
address byte and then adds this 16 bit offset to the content of PC.
• The BSR instruction causes the CPU to take three actions:
1. The CPU fetches the relative address accompanying the opcode.
2. The CPU stacks the PC value.
3, The CPU sign extends. the relative address and adds it to the
content of PC

• A sub routine is a program routine that reside in a block of memory


separate from the main program.
Conditional branching:
• There are 18 conditional branching instructions.
• BCC – branch if Carry Clear
• BCS -- branch if Carry Set
• BNE -- branch if Not Equal. Branch if Z=0
• BEQ -- branch if Equal. Branch if Z=1
• BPL -- branch if Plus, Branch if N=0
• BMI -- branch if Minus, Branch if N=1
• BVC -- branch if V flag Clear
• BVS -- branch if V flag Set
Four branching instructions specify conditions caused by subtract or
compare operations on unsigned operands. These are as follows:
• BHI –branch if higher. Branch if the unsigned minuend is higher than
the unsigned subtrahend. i.e; branch if both C and Z are reset
(C +Z=0).
• BHS – branch if higher or same. Same as BCC, i.e; branch if carry
flag is reset.
• BLO -- branch if lower. Same as BCS, i.e; branch if carry flag is set.
• BLS -- branch if lower or same. To make the branch either the C or
the Z flag must be set (C+Z=1)

The 4 signed operand oriented conditional branching are,


• BGT – branch if greater than, branch if Z=0 and N & V flags equal
(Z+(N exor V) = 0)
• BGE – branch if greater or equal. To make the branch N and V flags
must be equal (N exor V = 0)
• BLT – branch if less than. N and V flags must be unequal
(N exor V = 1)
• BLE -- branch if less than or equal. Either the Z flag musr be set or
the N and V flags unequal (z + (N exor V) = 1)

• BRCLR -- branch if bits clear


• BRSET -- branch if bits set
These includes a mask byte which accompany the instruction opcode.
This mask specifies the target memory bits to be tested. These
actually use 2 addressing modes. Relative mode specifies the
branch destination. Either direct or extended modeaccesses the
memory.
Eg: BRCLR 2A 88 128
$2A is the direct modeaddress to be tested($002A) and $88 is the
mask %10001000. $0128 is the branch destination address.
Program jump and Return instructions:
• JMP -- Jump. Store a new specified address to the PC.
• JSR – Jump to subroutine. Push the PC content to stack and store a
new specified address to the PC.
• RTS – Return from Subroutine. Pull an address from the stack and
restore it to the PC.

• JMP uses extended or indexed mode


• Eg: JMP C050, JMP 1A, X\
• JSR and BSR operate in the same manner. But there are two
differences:
1. BSR uses relative mode. JSR uses direct, extended or indexed mode.
Eg: JSR 2A stores the direct mode address $002A to PC
JSR FF27 stores the extended mode value $FF27 to the PC
Assume that the Y register contains $C000
JSR A,Y stores $C00A to PC
2. Because it uses 1 byte relative address, the BSR instruction can
redirect program flow up to 128 addresses back or 127 addresses
forward. A JSR instruction can redirect program flow to any address
on the M68Hc11’s memory map.

The last subroutine instruction must be RTS


Buffalo Rom System Commands:

• Memory Display (MD):


the MD command allows the user to display the hex contents of any
M68HC11 address on the terminal screen,
Examples:
MD
Buffalo displays 9 lines of memory starting at address $0000, 16 bytes
to a line and so 144 memory addresses.
$0000 - $000F
$0010 - $001F
|
|
|
$0080 - $008F
MD B604
BUFFALO displays starting with a 16 byte line which includes $B604
$B600 - $B60F
|
|
$B680 - $B68F
MD B735 B757
Displays 16 byte lines of memory inclusively from the line which
contains the address $B735 to the line which contains address $B757
$B730 - $B73F
$B740 - $B74F
$B750 - $B75F
MD B647 – B76A
scroll through the multiple line of 16 bytes each from the line which
contains the address $B647 to the line which contains address 4B76A
• Memory Modify (MM):
This allows the user to initialize operand or data bytes in RAM or
EEPROM. To modify the contents of a RAM or EEPROM location
(address $002A) use
MM 2A
In response, BUFFALO displays the address, its contents and a prompt
002A FF _

Using MM and space bar user can enter string of data/program bytes to
consecutive RAM/EEPROM locations.
• Block Fill (BF):
used to load a string of memory address with a constant value.
BF B60A B71D A1
loads addresses $B60A, $B71D and all intervening locationswith the
value $A1.
• MOVE Command:
used to copy the contents of block of addresses to RAM or EEPROM
MOVE 0 2A B700
copies the block of data with addresses from $0000 to $002A to the
block with starting address $B700

• Go (G) Command:
It causes the M68HC11 to execute program,
G B710
Executes the program which is stored at an starting address $b710. in
response to this PC is loaded with 4B710

• Assembler/Disassembler (ASM) Command:


The ASM command invokes the BUFFALO one line
assembler/disassembler. The assembler compiles source code into
machine code and the disassembler translates machine code back
into BUFFALO assembly code.
ASM 100
The no. 100 indicates the hex address at which you wish to begin
assembling the program. In response to this BUFFALO displays
100 STX $FFFF > _
The bytes displayed here indicates “power up”. The prompt here
indicates that you can assemble an instruction. Enter the source
code line by line and this command will assemble each line one at a
time.

Register Modify (RM):


This allows a user to examine the current contents of registers and
change their contents.
RM
This will display the contents of all registers in one line and in the second
line it will prompt for change, Space bar can be used to switch
between registers. To change the contents of a single register we
can enter as
RM B
This allows us to change ACCB

Trace Command (T):


Causes BUFFALO to display current CPU status each time it fetches and
executes a program instruction. After initializing PC we can enter
T
This will Execute one instruction display the CPU status, the succeeding
instructions can be executed by simply pressing return key after each
fetch and execute.
To trace 20 consecutive instructions
T 14
It will execute 20 instructions and display the status after each instruction
execution.
Breakpoint Set (BR) Command:
allows the user to execute a program up to the break point. The BR
command allows a user to establish up to 4 breakpoint addresses. To
establish breakpoint at $105 & $109 enter
BR 105 109
The user can then execute by G command. The CPU executes till the first
breakpoint and halts. To continue program execution use P command.
To erase all breakpoints
BR –

Proceed/Continue Command (P):


use P to continue after breakpoint
Assembler directives

Use the following prefixes to identify decimal, hex,


octal and binary numbers
No prefix – decimal (default, e.g., 5327)
$ -- hexadecimal (e.g., $1010)
@ -- octal (e.g., @527)
% -- binary (e.g., %10011010)
NAM (Name)– assign a title to the program on the first line
of the source code. Enter the NAM directive into the
operation field and then follow with a space and a title.
e.g., NAM sort. Here sort is the program’s name.

ORG (Origin) – establishes starting address for program


memory blocks. An ORG directive can establish the
starting address of a main program, a subroutine, an
interrupt routine, operand storage areas or results. Enter
the ORG mnemonic into the operation field and the
starting address into the operand field.
e.g., ORG $0100
If no ORG is used the assembler assumes that the
memory block begins at address $0000
EQU (Equate) – establish address or operand values and
assign labels to them. These values are not stored in the
memory. Enter the label in the label field, the EQU
mnemonic in the operation field and the value to be
assigned in the operand field.
e.g., count EQU $0A

FCB (Form Constant Byte) – labels a specified value and


assigns it to an M68HC11 memory location. So the
programmer will not know which memory byte has the
specified value. But a previous ORG directive can
establish a memory block in which the value will reside.
Enter the label in the label field, the FCB mnemonic in
the operation field and the value to be assigned in the
operand field.
e.g., num FCB $FF
If no value is specified the assembler stores 00 in the
memory location.
e.g., num FCB
We can also use the FCB directive to initialize an array of
bytes.
e.g., arr FCB 1,2,3,4,5
These values are stored in the consecutive memory
locations.
If there is no entry between two commas, 00 will be stored.
e.g., arr FCB 1,2,,3,4
This will store 1,2,0,3,4 in successive memory locations.
arr FCB ,, this will store 0 in all 3 memory locations.
FDB (Form Double byte) – functions in the same
way as FCB’s except that FDB’s store 2 bytes at
a time.
e.g. num1 FDB $9C10
This will store $9C in memory location num1 and
$10 in location num1+1
num1 FDB – will store 00 in two memory locations
num1 and num1+1
num1 FDB $9C10, -- will store $9C,$10,00,and
00in successive memory locations.
RMB (reserve Memory Byte) – labels and sets
aside a series of memory locations. This will not
initialize the memory locations. A previous ORG
directive can establish a memory block with in
which the memory bytes will reside. Enter the
label in the label field, the RMB mnemonic in the
operation field and the number of bytes to be
reserved in the operand field.
e.g., result RMB 15
BSZ (Block Storage of Zeroes) and ZMB (Zero Memory
Bytes) cause identical responses. These operate in
manner identical to RMB except that 00 is stored in all
memory bytes.
e.g., result ZMB 20

FILL (Fill Memory) – label, reserve and fill a specified no. of


memory bytes with the specified value. Enter the label in
the label field, the FILL mnemonic in the operation field
and two values, separated by comma, in the operand
field. The first value is the initialization value and the
second value is the no. of bytes to be reserved and
initialized.
e.g., result FILL $FF,20
This will reserve a series of 20 memory locations and
initialize them all to $FF
FCC (Form Constant Character String) – label and
store an ASCII string into a series of memory
locations. Enter the label in the label field, the
FCC mnemonic in the operation field and the
ASCII string in the operand field. Prefix the string
with a delimiter and add a suffix delimiter at the
end of the string. Use identical delimiters. The
allowable delimiters are comma, colon and
semicolon. Assure that the string includes only
printable ASCII characters.
e.g., prompt FCC ;password;
This will store the string “password” in series of
memory locations.
M68HC11 RESETS AND INTERRUPTS

• Resets cause the microcontroller to abort its normal fetch and


execute, then prepare to start again. Resets occur because the user
wants to start program execution over again or something has gone
wrong.

• Interrupt is a signal which deviates the normal execution of the


processor. Interrupts cause the CPU to save the status and service
the interrupt. After servicing the interrupt, the CPU can resume the
routine fetch and execute from where it left off.
M68HC11 RESETS:
M68HC11 resets when its RESET pin goes low and then high.
During reset M68HC11 takes some actions when its RESET pin
first goes low and it takes further actions when its RESET pin is
then driven high. Four situations can affect RESET pin levels.
1. An external circuit drives the RESET pin low then high
2. An internal circuit detects a chip power up, and drives the RESET
pin low, then high.
3. An internal circuit detects slow or stopped M68HC11 clocks. If the
clocks are slow but not stopped, the internal circuit drives RESET
pin low, then high. If clocks are stopped, the internal circuit drives
RESET pin low, but may not be able to drive it back high.
4. An internal circuit detects that CPU appears to be lost or hung up

When an external or internal circuit drives RESET pin low, the


M68HC11 automatically establishes its memory map and disables
most of its interrupts internal hardware functions. When RESET pin
rises from low to high, the CPU vectors to a reset service routine
provided by the system designer.
In the 1st and 2nd case above the CPU vectors to an initialization routine.
In the 3rd and 4th case above the CPU vectors to special emergency
routine.
RESET Generation:
Resets are generated in 4 ways.
To generate external h/w reset, the RESET pin must remain low for 6
E clock cycles before rising back high. This can be done by using
push-button pull-up circuit, and an under voltage sense circuit. This
is shown in the following figure.
Pull-Up Circuit
Vdd
Vdd
2 R1 47K M68HC11
MC34064P 1 17 RESET
3
Under voltage SW1
Sensor
The user can reset the M68HC11 by first pressing the push-button
and then releasing it. The under voltage sensor drives the RESET pin
low when it senses a significant drop in Vdd.

If the M68HC11 powers up, it automatically resets (Power On Reset-


POR). An on board POR circuit detects Vdd pin’s rise from 0 volt and
drives RESET pin low for 4064 E clock cycles

If M68HC11 clocks slow down an internal clock monitor reset circuit


can drive the RESET pin low for 4 E clock cycles then back high.
User can enable or disable this clock monitor by writing a bit to the
Systems Configuration Options Register (OPTION). The OPTION
register resides at address $1039

IRQE DLY CME CR1 CR0

B3
OPTION Register
• CME bit – 1  enable, 0  disable the clock monitor detect circuitry.
• Any chip reset clears the CME bit, so only program instruction can
enable the clock monitor detect circuitry.
• If internal clocks have completely stopped, the RESET remains low
and will not go back high. In such cases the CPU cannot vector to a
service routine. Then the user has to correct it.

• During the 6th E clock cycle after the RESET pin was driven low, the
M68HC11 checks it again. If it is still low, the M68HC11 assumes that
a POR or external circuit caused the reset. If it returned high before 6
E clock cycles have elapsed, the M68HC11 assumes that the clock
monitor has detected slow clock or that the CPU is lost. In this case
the M68HC11 makes further check to determine whether the clock
monitor caused the reset. If so the CPU vectors to an appropriate
reset response routine.
The computer operating properly (COP) system forms the 4th reset
source. This system detects “hung up” or lost M68HC11 CPU and in
such cases it drives RESET pin low for 4 E clock cycles, then driving
back high.

The COP system uses a timer. This timer operates when the COP is
enabled and the CPU executes program instructions. With the COP
enabled the CPU must write $55 and then $AA to a control register
before the timer times out. If not the COP causes reset. Writing these
causes the timer to begin a new time out.

The COP system uses bits in 3 control registers: CONFIG,OPTION


and COPRST. An user enables the COP system by clearing a bit in
the CONFIG register. It’s address is $103F.

NOCOP
B2
CONFIG REGISTER
To enable the COP system, the user must reset the NOCOP bit. The
reader cannot program the CPU to write a zero to NOCOP, and
thereby turn on the COP system. Rather, MOVE a control byte from
RAM to CONFIG, using the BUFFALO MOVE command. As long as
NOCOP remains reset, the COP system operates every time the
M68HC11 executes a program. Two bits in the OPTION register give
the system designer a choice of four timeout periods. Motorola calls
these bits the COP timer rate select bits, CR1 and CR0. The four
COP timeouts derive from the M68HC11’s E clock. Internal clock
divider divide the E clock frequency by 215. This E/ 215 frequency
feeds the COP timer. CR1/CR0 bit settings cause the COP timer to
divide the E/ 215 frequency by 1, 4, 16, or 64.

CR1 CR0 E/ 215 divided by


0 0 1
0 1 4
1 0 16
1 1 64
• The M68HC11 time protects OPTION register’s CR1/CR0 bits. The CPU
must write to time protected bits within sixty four bus cycles after a chip
reset. Thus, M68HC11 must initialize CR1/CR0 as part of its POR/external
circuit reset service routine.
• Figure below illustrates program flow with COP enabled. After writing $AA
to COPRST, the M68HC11 must execute application program instructions,
return, and execute blocks 1 & 2, before COP timeout.

Program Flow
NOCOP = 0

1. Write $55 to COPRST

2. Write $AA to COPRST

3. Execute application
program instructions
Reset Actions:
M68HC11 takes the following actions when it’s RESET pin is driven
low:

1. It completes establishment of its memory map by initializing the RAM


and I/O Mapping Register (INIT, control register block address $103D)
to $01.

B7 B6 B5 B4 B3 B2 B1 B0

RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0

RESET = 0 0 0 0 0 0 0 1
INIT REGISTER

INIT register bits B7 – B4 establish the upper hex digit of M68HC11


internal RAM addresses.
When RESET goes low, the M68HC11 forces this digit to zero. This
action locates internal RAM at address block $0XXX.

INIT register bits.B3-B0 (REG3-REG0) establish the upper hex digit


of control register block addresses. When RESET goes low, the
M68HC11 forces REG3-REG0 to %0001. Thus, the M68HC11’s
internal control and status registers reside at memory locations
$1000-$103F.
2. The M68HC11 forces the contents of its PIOC (Parallel I/O Control
register) to %00000X11. this will disable all parallel I/O associated
interrupts.
3. The M68HC11 initializes the counter in its timer system to $0000 and
disables all timer associated functions and interrupts.
4. Depending upon the state of the NOCOP bit in the CONFIG register,
COP system is enabled or disabled.
5. The M68HC11 disables the serial I/O systems and their associated
interrupts.
6. The on board ADC is disabled
7. Interrupt parameters and priorities are set, but all interrupt
mechanisms are disabled except for illegal opcode traps.
8. The clock monitor system will be disabled.

Overall the M68HC11 initializes bits in 24 control registers when its RESET
pin is driven low. These bits establish most of the conditions listed
above.

When the RESET pin rises from low to high the CPU copies the address of
an appropriate reset service routine to its program counter then
executes that routine. These reset routines are loaded at addresses
$E000,$00FA and $00FD. The addresses for different routines are as
follows:
POR/external circuitry --- $E000 (in ROM).
Clock monitor system ---- $00FD (RAM).
COP system ----- $00FA (RAM).
These addresses are copied to the PC from ROM. Three pairs of ROM
locations contain these addresses:
1. $FFFE and $FFFF ----- $E000.
2. $FFFC and $FFFD ----- $00FD.
3. $FFFA and $FFFB ------ $00FA.
in the case of clock monitoring & COP reset the BUFFALO O. S.
uses pseudovectors. Pseudovector is a JMP instruction which re-
vectors the CPU to the ISR’s starting address
INTERRUPTS:

• Types:
• 12 types are there. 7 are special purpose and 5 are general
purpose.
1. Serial Communication Interface uses SCI Serial System interrupt.
Used for a variety of control or error detection purposes.
2. Serial Peripheral Interface (SPI) facilitates synchronous two way
data exchanges between microcontroller and external devices. The
SPI uses SPI Serial Transfer Complete Interrupts to control data
transmission over SPI lines
3. The M68HC11’s pulse accumulator counts the no.of times an
external device applies specified rising and/or falling edges to an
input pin. A Pulse Accumulator Input Edge Interrupt occurs each
time the external device applies a specified edge to the pulse
accumulator’s i/p pin.
4. The Pulse Accumulator maintains its i/p edge count in a special 8 bit
register. Pulse Accumulator Overflow Interrupts can interrupt the
CPU each time the count register’s 8 bit contents roll over from $FF
to $00.
5. The M68HC11 incorporates a flexible and sophisticated timer
section. This timer section bases a wide variety of functions on a 16
bit, free-running counter. The Timer Overflow Interrupt can interrupt
the CPU each time the free-running count rolls over from $FFFF to
$0000.
6. The M68HC11’s timer section includes an Output Compare feature.
Output compare mechanisms compare 16 bit values, established by
the user, with the free-running count, each time this count
increments. When a match occurs, the o/p compare mechanism
drives an assigned o/p pin to a user-specified level.
7. The M68HC11’s timer section also includes Input Capture
mechanisms. Each i/p capture mechanism monitors an assigned
M68HC11 i/p pin. When a peripheral drives this pin with a specified
edge, the i/p capture mechanism records the free-running count.
Each i/p capture mechanism includes an I/p Capture Interrupt.
When enabled, an I/p capture mechanism interrupts the CPU when
it detects a specified edge at its assigned pin.

The above 7 types are special purpose interrupts. The rest are the
general purpose interrupts.

8. The M68HC11 generates an interrupt when the CPU fetches an


illegal opcode.
9. The Real Time Interrupt (RTI) mechanism generates recurring
interrupts at a periodic rate selected by the user. When interrupted,
the CPU vectors to a user- developed, RTI interrupt service routine.
The user can select from four periodic RTI rates derived from the E
clock frequency.
10. The SWI (Software Interrupt) instruction causes the CPU to vector
to a user defined custom routine. SWIs provide a useful alternative
to a subroutine call (JSR, BSR). A subroutine call saves only PC
but an interrupt saves entire processor context.
11. By driving M68HC11’s IRQ pin low, an external device can
generate an IRQ interrupt. Parallel I/O handshake signals can also
generate an IRQ interrupt.
12. By driving M68HC11’s XIRQ (pseudo nonmaskable interrupt
request) pin low, an external device can cause the CPU to stack its
context and vector to a custom XIRQ service routine.
Global and Local interrupt Masks:

A user cannot disable illegal opcode traps. The user generates s/w
interrupts by writing an SWI instruction into the program. Of the
remaining 10 interrupt types all are maskable at the global level
(CCR), and nine are also masked locally by bits in control registers.

The CCR’s X bit masks XIRQs globaly. Any M68HC11 reset sets X
to 1 and X=1 inhibits XIRQ interrupts. S/w can enable XIRQ
interrupt by resetting X to 0. But s/w cannot change X from 0 to 1.
So once enabled it cannot be disabled except by resetting the
microcontroller. So XIRQs are Pseudo Nonmaskable interrupts. The
TAP instruction can be used to reset X bit.
The M68HC11 masks the following interrupts at both the global and
local levels.
• SCI Serial System Interrupts
• SPI Serial Transfer Complete Interrupts
• Pulse Accumulator Input Edge Interrupts
• Pulse Accumulator Overflow Interrupts
• Timer Overflow Interrupts
• Timer Output Compare Interrupts
• Timer input Capture Interrupts
• Real Time Interrupts (RTI)
• Interrupt requests (IRQ)

The CCR’s I bit (bit 4)enables and disables these interrupts at the
global level. Clearing the I mask enables these interrupts and setting
the I mask disables them.
A user can use the instructions SEI and CLI to set or clear the I
mask

IRQ interrupts can be generated in two ways.


1. By a low level at IRQ pin
2. By a parallel I/O handshake signal

Only the I bit can mask IRQ generated interrupts. IRQs generated
by the parallel I/O mechanisms are masked locally and by global I
mask

Interrupt Vectors and BUFFALO ROM Pseudovectors:

Each ISR has an assigned starting address The M68HC11 copies


the service routine starting address to its PC from storage locations
$FFD6 - $FFF9 in ROM. Upon POR or push button reset,
BUFFALO O.S. stores default pseudovectors to all ISR starting
addresses in RAM. Pseudovector is a JMP instruction which re-
vectors the CPU to the ISR’s starting address
The Interrupt Stack and RTI instructions:

• All 12 interrupts cause the CPU to stack its context. Suppose SP


contains $0048 at the time of interrupt
$003F ------
$0040 CCR
$0041 ACCB
$0042 ACCA
$0043 X register – MS
$0044 X register - LS
$0045 Y register - MS
$0046 Y register - LS
$0047 PC - MS
$0048 PC - LS
• After each context byte is stacked the SP is decremented by 1
• What happens if you have nested interrupts?
• Stack overflow
• The M68HC11 includes 2 features to prevent nested interrupts. In the
case of all interrupts the M68HC11 automatically sets the I mask as
soon as the CPU has finished stacking processor context. To permit
nested I maskable interrupts the CPU must execute CLI instruction as
part of the ISR. During I maskable interrupts the M68HC11 does not
automatically set the X mask. So a peripheral could generate an
XIRQ interrupt while the CPU executes an I maskable ISR. In the
case of XIRQ interrupts the M68HC11 automatically sets both I and X
masks as soon as the CPU has finished stacking processor context.

• The last instruction in the ISR is RTI. An RTI instruction causes the
CPU to pull its original context from the stack and restore all registers
to their original conditions - at the time the interrupt was generated.
When pulling data from the stack, the M68HC11 increments the SP
by 1 then pulls a byte from the stack.
I Maskable Interrupt Priorities:

• Illegal opcode, SWI and XIRQ have supreme priority since they are
nonmaskable. The user can program the CPU to promote any other
interrupt to highest I maskable interrupt. The promotion routine must
set the I mask, write promotion bits to the HPRIO register, then reset
the I mask to permit interrupts.
B3 B2 B1 B0
PSEL3 PSEL2 PSEL1 PSEL0

HPRIO REGISTER $103C


To promote to highest priority the CPU writes a unique bit
combination to HPRIO Priority Select bitsPSEL3 – PSEL0. for
example to promote Timer Overflow Interrupt to top priority the CPU
clears all PSEL bits
SEI
CLRA
STAA 103C
CLI

The first instruction sets the I mask. The PSEL bits are not writable
unless I = 1, inhibiting I maskable interrupts.

WAI and STOP instructions:

In some applications the microcontroller has no routine business to


execute the CPU has nothing better to do than wait for a device to
request service. Under such circumstances the programmer can use
the WAI and STOP instructions. Both instructions cause the
microcontroller to reduce power consumptions.
WAI instruction execution
SCI Rx disabled? no
yes
Stack CPU context
Power down SCI Rx

I=1 and
COP SCI Tx disabled?
no no
disabled?

yes yes
Power down timer section Power down SCI Tx

SPI disabled? no CPU to wait state

yes Do address data bus read


Power down SPI circuits cycle to SP-8 location
Recovery from WAI

Turn on powered down circuits

Set I and X masks as appropriate

Copy appropriate interrupt routine


address from ROM to PC

Execute interrupt service routine


• The STOP instruction can act as an NOP or it can stop the
microcontroller causing a reduction in power consumption. If it acts as
an NOP it merely takes 2 m/c cycles and processing proceeds to the
next instruction. If stopped it stops all internal clocks
• If S = 1  NOP
• If S = 0  halts processing
• TAP instruction can be used to set or reset S bit.
• The M68HC11 recovers from STOP if either (1). an external circuit
drives RESET or XIRQ pin low; or (2). when I=0 and an external
device drives the IRQ pin low.
STOP Execution

yes
S=1?

no
Stop all internal clocks
Resume fetch and execute
STOP Recovery

yes
DLY=0?
no yes
X=1?
Delay for 4064 E clock
cycles(OSC stabilization)
no

Process XIRQ interrupt


yes
XIRQ low?

no

Process IRQ interrupt Fetch and execute starting


with next instruction

DLY – bit 4 in OPTION reg. Enable Oscillator Start Up Delay --- on exit from STOP
• Any reset establishes the DLY bit’s default condition as zero.

• But M68HC11 might have to execute critical timing sequences


immediately upon its recovery from STOP. In such a case the
POR/external circuit reset service routine should set the DLY bit.
IRQ Pin – Generated Interrupts:

A programmer has the option of making IRQ interrupts level sensitive


or edge sensitive. To make IRQs edge sensitive , the CPU sets the
IRQE bit in the OPTION register. To make IRQs level sensitive , the
IRQE bit must be clear. All M68HC11 resets clear the IRQE bit. Thus,
by default, a low level at the IRQ pin generates an IRQ interrupt.

If IRQE=1, making IRQs edge-sensitive, IRQ interrupt control logic


latches falling edges at the IRQ pin. IRQ control logic remains in this
latched state until the M68HC11 actually services the interrupt. If
IRQE=0,making IRQs level-sensitive, an external peripheral must hold
the IRQ pin low until the M68HC11 responds. Otherwise, the
M68HC11 will never recognize the interrupt request.
IRQ Demonstration:
5V MAIN

Initialize SP
4,7K
19 IRQ Initialize IRQ pseudovector

M68HC11
Clear location $0000

Clear I mask

IRQ Call delay

Increment location $0000

Call delay

Return
Main ISR
LDS #1FF 0120 INC 0
LDD #120 JSR 130
STD EF RTI
CLR 0
CLI DELAY
010C JSR 130
BRA 10C Load loop counter (ACCA) with $06

Load x register with $D600


DELAY
0130 LDAA #6 Decrement x register
9132 LDX #D600
0135 DEX yes
X reg not 0
BNE 135
no
DECA
Decrement loop count
BNE 132
RTS Loop count not 0
yes
no
Return
XIRQ Interrupts:

• Motorola developed XIRQs to replace NMIs two solve two problems.


Problem 1. In most of the applications the POR/external pin reset
service routine initializes the SP with RAM address. One can not
predict the SP’s content prior to this initialization; the SP might be
pointing at important data or program bytes. With NMIs a peripheral
can generate an NMI at any time. Then the processor context may
be stacked over important data or program bytes. XIRQs prevent
this problem because the M68HC11 masks them as part of its initial
actions. Thus XIRQs are inhibited until software clears the X mask.
Problem 2. Because NMIs are nonmaskable it is to nest them. If the
peripheral’s NMI request bounces – three times for example – it
generates three nested NMIs. XIRQs prevent this problem because
the M68HC11 automatically set the X mask upon its entry into the
XIRQ service preventing nested interrupts.
• Once s/w clears the X bit, it cannot set it again. Only reset or XIRQ
interrupt itself causes the X bit to set. In the case of an XIRQ interrupt
the RTI execution in the XIRQ routine clears the X bit. Thus XIRQs are
unmasked again.
• XIRQ supporting s/w uses interrupts to record either the no. of times
or the no. of seconds user presses the push button

5V

4.7K
18 XIRQ

M68HC11
MAIN(WAI) MAIN(STOP)

Initialize SP Initialize SP

Initialize XIRQ pseudovector Initialize XIRQ pseudovector

Clear location $0000 Clear location $0000

Clear X mask Clear S and X mask

Wait for interrupt Stop internal clocks

• The CPU executes WAI instruction by stacking its context, powering


down unused timer SCI and SPI circuits and entering into a wait state.
When an XIRQ interrupt causes recovery from WAI, the CPU sets the
X and I masks and then vectors to the XIRQ service routine. The CPU
executes STOP by turning off all of its internal clocks and when an
XIRQ interrupt causes recovery from STOP, the CPU stacks its
context, sets X and I masks, then vectors to the XIRQ interrupt service.
LDS #COFF LDS #COFF
LDD #C040 LDD #C040
STD F2 STD F2
CLRA CLRA
STAA 0 STAA 0
TAP TAP
C00C WAI C02C STOP
BRA C00C BRA C02C

C040 INC 0
XIRQ
LDAA #6
C045 LDX #D600
Increment location counter C048 DEX
BNE C048
Execute one second delay
DECA
BNE C045
RTI
Return
Illegal Opcode Interrupts:

• The M68HC11 stacks its context and vectors to a special routine


when it fetches an illegal opcode.

MAIN Decrement X register

Initialize SP X reg not 0?


yes
no
Initialize ILLOP pseudovector
A Decrement delay loop count
NOP
NOP

Initialize delay loop counter(ACCA) yes


Loop count not 0? A
B
NOP no
NOP
Load X register with count down value
Call .OUTRHL
NOP

NOP A
• The CPU calls the BUFFALO .OUTRHL utility subroutine. This
subroutine converts ACCA’s low nibble (0) to ASCII and writes it to
the terminal display. After displaying 0 the CPU executes another 1
second delay.
• If it encounters an illegal opcode while executing the MAIN program
the CPU vectors to the ILLOP ISR at address $0130. ILLOP causes
the CPU to display on the terminal screen ILLOP @ $XXXX
where $XXXX is the program address of the illegal opcode.

• The ILLOP ISR uses the BUFFALO .OUTSTR utility subroutine to


display ILLOP<sp>@<sp>$<EOT> (EOT  End Of
Transmission). This subroutine causes the CPU to write successive
ASCII bytes (pointed at by the X register) from RAM to the terminal
screen, until it encounters the EOT code. Then to display the address
of the illegal opcode the X register is pointed at by the address which
contains this address and the BUFFALO .OUT2BS subroutine is
called. This subroutine displays the contents of the memory location
pointed at by the X register.
• .OUT2BS execution writes over the contents of ACCA. Before
returning from ILLOP the CPU must increment the stacked PC value
because when the CPU encounters an illegal opcode, it stacks a PC
value pointing directly at the illegal opcode location. Therefore the
CPU must re read the stacked PC value to the D register.

ILLOP

Point X reg, at PC value in RAM


Point X reg. to error message

Call .OUTSTR Call .OUT2BS

Transfer SP+1 value to the Y reg. Copy stacked PC value to D reg.

Increment PC value to point at next


Copy stacked PC value to D reg.
MAIN program instruction,
(ILLOP location)

Store PC value to RAM Store incremented PC value to stack location

Return
A Software Interrupt Demonstration:

• SWIs become an alternative to subroutine calls when the MAIN


program and routine to be called use different processor contexts.

• The example here calculates totals for 4 operand groups, 5


operands in each group. The MAIN program transfers each operand
group in turn to 5 memory locations. After transferring an operand
group the MAIN calls an SWI. The SWI routine finds the total of the
operands and stores the total in an assigned memory location.
MAIN

Initialize SP
Compare X reg with address of
Initialize SWI pseudovector ADDOP5+1

Point YTEMP at SUM! yes


Not equal A
Point Y reg. at GROUP! no
B
Call SWI
Point X reg at ADDOP!
A
Load ACCA with next operand Compare Y reg with address of
from GROUPx (pointed at by the last GROUP4 operand + 1
Y reg

yes
Store next operand to ADDOPx Not equal B
(pointed at by X reg.
no
Halt
Increment X and Y reg
SWI

Load Y reg from YTEMP

Point X reg at ADDOP1

Clear SUM accumulator

Add next operand to be added

Increment X reg Store sum to location pointed at by Y reg

Compare X reg with address of


ADDOP5+1 Increment Y reg and store to YTEMP

yes
no return
Not equal
PARALLEL I/O

The M68HC11 has the following resources for implementing parallel i/o.
• PORTB data register. It drives output pins PB0-PB7. this is an
output port only.
• PORTC data register. This port can be configured as either input or
output.
• Data Direction Register for PORTC(DDRC). This is used to
configure PORTC pins as input or output bits. Writing a 1 to a DDRC
bit configures the corresponding PORTC pin as an output. Writing a
0, configures as input. With a system reset all DDRC bits reset and
configure all PORTC pins as inputs.
• PORTA and PORTD can also be used for general purpose parallel
I/O
Parallel I/O program flow:

Read PORTB: Write to PORTB:

Read PORTB Write PORTB

Read PORTB data Load accumulator with


to an accumulator. Write data

Store or manage Write data from


PORTB data accumulator to PORTB

Read complete Write complete


• Read PORTC:

Read PORTC
PC3-PC0

Initialize DDRC to
Configure PC3-PC0 as inputs
And PC7-PC4 as outputs

A PORTC read returns previous write data from


Read PORTC data
pins PC7-PC4. these data bits are made zero
to an accumulator.
after a PORTC read.

Delete PC7-PC4 read data

Store
PORTC read data

Read complete
Write to PORTC:

PORTC parallel I/O

Initialize DDRC to
Configure PC3-PC0 as inputs
Write PORTC
And PC7-PC4 as outputs

Read PORTC
Load PORTC
Write data
Read PORTC data
to an accumulator.
Write data to PORTC

Delete PC7-PC4 read data


Write complete
Store
PORTC read data
A PORTC data write routine
immediately follows the PORTC
Read complete read
M68HC11 EXPANDED MULTIPLEXED MODE

Expanded multiplexed mode allows the user to expand directly


addressable memory by as much as 16K bytes. To expand memory
the user interfaces external memory chips with the M68HC11’s
address data and control buses.

Address and data buses are connected to PORTB and PORTC pin. Thus
in this mode PORTB and PORTC pins cannot be used for parallel I/O

PORTB – 8 MS bits of address bus


PORTC -- 8 LS bits of address and 8 bits of data bus

In expanded multiplexed mode control signals are connected to STRA


and STRB pins
Resources used for expanded multiplexed mode

• To enter and operate in expanded multiplexed mode the M68HC11


uses one control register and 21 pins. Four control register bits
cause the M68HC11 to enter expanded multiplexed mode. At the
time of reset two external pins set/reset these control bits. The
remaining 19 pins serve as control, data and address bus pins.

MODEA/MODEB Pins and HPRIO Register:

Four bits in the HPRIO register put the M68HC11 into one of four
hardware modes.
HPRIO High Nibble Bit values Hardware mode
%0000 Single Chip
%0010 Expanded Multiplexed
%1101 Special Bootstrap
%0111 Special Test

Single Chip Mode: In this mode the M68HC11’s s/w resides in on chip
memory. The address and data buses are also internal and unavailable
to external devices,
Expanded Multiplexed Mode: In this mode the M68HC11 connects its
address and data buses , read/write line and an address strobe to
external pins. Expanded mode allows the user to connect external
extended memory for applications requiring large amounts of s/w and
data storage.
Special Bootstrap Mode: In this mode instead of vectoring to a reset
routine, the M68HC11 automatically uploads a 256 byte user program
via its SCI and executes this program. Motorola designates bootstrap
as a special version of single chip mode.
However the M68HC11 CPU can connect its internal buses to external
pins as a part of the uploaded bootstrap program.
Special Test Mode: This mode facilitates production testing of M68Hc11
chips. This mode overrides a number of on chip protective
mechanisms.

HPRIO Register

RBOOT SMOD MDA IRV

B7 B0

The RBOOT (Read Bootstrap ROM) enables a special routine in the on


board ROM. The ROM routine causes the CPU to import a special
bootstrap program via the SCI and then execute it. RBOOT = 1
enables this ROM and RBOOT = 0 disables it.
When set the SMOD (Special Mode) either causes the CPU to execute
the special bootstrap ROM routine upon reset or puts the
microcontroller into
special test mode depending on other high nibble HPRIO bits. If
SMOD = 0 the M68HC11 takes neither action but instead operates in
either single chip or expanded multiplexed mode depending on other
high nibble HPRIO bits.
The MDA (Mode A Select) bit determines whether the M68HC11
connects its internal buses to external pins. MDA=1 connects internal
buses to external pins. MDA=0 internal buses are not connected to
external pins.
The IRV (Internal Read Visibility) causes internal read data to appear on
external data bus pins. If IRV=1 and MDA=1 , internal read data
appear externally. If IRV=0 or MDA=0, internal read data cannot
appear on externally. IRV can equal to 1 only when SMOD=1
CPU can write to these bits under the following conditions;
RBOOT: When SMOD =1
SMOD: CPU can write a 0 only.
MDA: When SMOD = 1
IRV: When SMOD = 1
M68HC11 pins M68HC11 H/W HPRIO Bits
MODB MODA Mode RBOOT SMOD MDA IRV
0 0 Special Bootstrap 1 1 0 1
0 1 Special Test 0 1 1 1
1 0 Single Chip 0 0 0 0
1 1 Expanded Multiplexed 0 0 1 0

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