Академический Документы
Профессиональный Документы
Культура Документы
ARM Basic
Von-Neumann and Hardward Architecture
Computer Performance
1. It is totally based on the CPU time
2. Cpu time is depend on how much time cpu need to execute a program.
3. It is totally depend on total number of cycles , instruction and program
also.
CPU Time = Time / Program
Time / program =
(Time / Cycle)*(Cycle/Instruction)*(Instruction/Program)
What Is ARM?
• Architectural simplicity
which allows
• Very small implementations
which result in
• Very low power consumption
The History of ARM
• Enhancements:
• Each instruction controls the ALU and
shifter
• Auto-increment
and auto-decrement addressing modes
• Multiple Load/Store
• Conditional execution
ARM Architecture (3)
• Results:
• High performance
• Low code size
• Low power consumption
• Low silicon area
Pipeline Organization
• Increases speed –
most instructions executed in single
cycle
• Versions:
– 3-stage (ARM7TDMI and earlier)
– 5-stage (ARMS, ARM9TDMI)
– 6-stage (ARM10TDMI)
ARM Pipeline Execution
Pipeline Organization (3)
• 5-stage pipeline: • Stages:
– Reduces work per cycle =>
allows higher clock frequency Fetch
– Separates data and Decode
instruction memory =>
reduction of CPI Execute
(average number
of clock Cycles Per Instruction) Buffer/data
Write-back
•
The Registers
ARM has 37 registers all of which are 32-bits long.
1. Supervisor Mode
2. Fast Interrupt Request:
3. Interrupt Request
4. Abort
5. Undefined
6. System
7. User
Operating Modes
• Seven operating modes:
– User
– Privileged:
• System (version 4 and above)
• FIQ
• IRQ
• Abort exception modes
• Undefined
• Supervisor
18
Operating Modes (2)
Exception modes:
User mode: – Entered
upon exception
– Normal program
execution mode – Full access
to system resources
– System resources
unavailable – Mode changed freely
– Mode changed
by exception only
Exceptions
Exception Mode Priority IV Address
Reset Supervisor 1 0x00000000
Undefined instruction Undefined 6 0x00000004
Software interrupt Supervisor 6 0x00000008
Prefetch Abort Abort 5 0x0000000C
Data Abort Abort 2 0x00000010
Interrupt IRQ 4 0x00000018
Fast interrupt FIQ 3 0x0000001C
• Special roles:
– Hardware
• R14 – Link Register (LR):
optionally holds return address
for branch instructions
• R15 – Program Counter (PC)
– Software
• R13 - Stack Pointer (SP)
ARM Registers (3)
cpsr
spsr
spsr spsr spsr spsr spsr spsr
Exception Handling
• When an exception occurs, the ARM:
– Copies CPSR into SPSR_<mode>
– Sets appropriate CPSR bits 0x1C FIQ
• Change to ARM state 0x18 IRQ
• Change to exception mode 0x14 (Reserved)
• Disable interrupts (if appropriate) 0x10 Data Abort
– Stores the return address in LR_<mode> 0x0C Prefetch Abort
0x08 Software Interrupt
– Sets PC to vector address
0x04 Undefined Instruction
• To return, exception handler needs to: 0x00 Reset
– Restore CPSR from SPSR_<mode> Vector Table
– Restore PC from LR_<mode> Vector table can be at
0xFFFF0000 on ARM720T
This can only be done in ARM state. and on ARM9/10 family devices
Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0
N Z C V Q JU n d e f i n e d I F T mode
f s x c
cpsr
spsr spsr spsr spsr spsr
3. Eg. When you switch to IRQ mode , then the subset of the
4. Each mode having its own stack space and and different
subset of register.
Banked out register
f s x c
Condition code flags T bit
N = Negative result from ALU T = 0: Processor in ARM state
Z = Zero result from ALU T = 1: Processor in Thumb state
C = ALU operation carried out J bit
V = ALU operation overflowed J = 1: Processor in Jazelle state
Mode bits
Specify the processor mode
Sticky Overflow flag - Q flag
Indicates if saturation has occurred
Interrupt Disable bits
I = 1: Disables IRQ
F = 1: Disables FIQ
SIMD Condition code bits - GE[3:0] E bit
Used by some SIMD instructions E = 0: Data load/store is little endian
E = 1: Data load/store is big endian
A bit
IF THEN status bits - IT[abcde] A = 1: Disable imprecise data aborts
Controls conditional execution of Thumb
instructions
Thanks