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SYNCHRONOUS BUCK
CONVERTER
NAME: CHAITRA.J
USN NO: R15MPE01
GUIDE: PROF.VISHWANATHA.V
Digital processors also have the advantage of being less susceptible to aging
and environmental or parameter variations. In addition, the processor can
monitor the system, perform self-diagnostics and tests, and communicate status to
a display or a host computer.
Non linear phenomena of a synchronous buck converter in continuous
conduction mode (ccm) is discussed.
The two quantizers like ADC ,DPWM are characterised by describing function
method and these will introduce limit cycle oscillations due to quantization effects
and need to be avoided.
SCHOOL OF ELECTRICAL ENGINEERING 3/15/2018 3
OBJECTIVES
Improved efficiency
Low losses
Low thermal dissipation
Highly reliable
In this digital control feedback circuit consists of a ADC and DPWM block
which are used to get output voltage in a desired manner.
[1] A. V. Peterchev and S. R. Sanders, “Quantization resolution and limit cycling in digitally
controlled PWM converters,” IEEE Trans. Power Electron., vol. 18, pp. 301-308, January 2003.
[2] H. Peng, A. Prodic, E. Alarcon and D. Maksimovic, “Modeling of Quantization Effects in Digitally
Controlled DC–DC Converters,” IEEE Trans. Power Electron., vol. 22, pp. 208-215, January
2007.
[3] S. Saggini, W. Stefanutti, D. Trevisan, P. Mattavelli and G. Garcea,“Prediction of Limit-Cycles
Oscillations in Digitally Controlled dc-dc Converters using Statistical Approach,” 31st Annual
Conference of IEEE Industrial Society (IECON’05), November 2005.
[4] X. T. Zhang, X. K. Ma and H. Zhang, “Low-frequency oscillation in digitally controlled DC-DC
17
Buck converters,” Acta Phys. Sin. vol. 57, pp. 6174-6181, October 2008.
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