UART USING SPARTAN FPGA

Department of Electronics and Communication Engineering

Presented by
G.SRINIVAS(314126512038)
D.ASHOK VARDHAN(314126512028)
G.J.M.RAVINDRA NAIDU(314126512048)
CHANDRAGIRI.RAM SAIKIRAN(314126512020)
Under The Guidance Of
S.BALARAM MURTHY
(ASSOCIATE PROFESSOR )
CONTENTS:
 ABSTRACT
 MOTIVATION
 INTRODUCTION
 METHODOLOGY
 SOFTWARE /HARDWARE
 WORK PLAN
 REFERENCES
 ABSTRACT
 UART(Universal Asynchronous Receiver
Transmitter) controller is a serial communication
device
 The function of UART is parallel to serial
conversion when transmitting and serial to
parallel conversion when receiving
 The sender and receiver have separate
,unsynchronised clock signals
In order to synchronize unsynchronized serial data
and to ensure that data integrity UART is used by
appending start and stop bits to the serial data.
The top level design of UART consists of a
clock generator, a receiving and sending
FPGA is a Field-Programmable Gate Array
which contains an array of
programmable logic blocks
We are going to do FPGA realization of
micro programmed implementation of UART
controllers.
MOTIVATION
 INTRODUCTION
• UART(Universal Asynchronous Receiver and
Transmitter):
A serial communication protocal that sends
parallel data through a serial line.
Typically used with RS-232 standards
• FPGA(Field Programmable Gate Array):
FPGA boards have an RS-232 port with a
standard nine pin connector.
METHOLODOGY
 UART TRANSMITTER
 UART transmitter consists of two main building
blocks data path unit ,control unit.
 Architecture consists of data ,data shift ,status
registers
 Input signal is provided by the host device,
output signals are the serial data stream and a
status signal.
 Data is transmitted serially on the serial output.
cont`d.
Transmitter transmits only when the status
signal is high.
When data ready is asserted high, the
transmitter loads the content of the data into
data register.
The assertion of load shift register loads the
contents of data register into shift register.
 UART CLOCK GENERATOR
To generate UART transmitter clock and
receiver sample clock.
Baud rate divisor for transmitter clock=system
clock/baud rate.
Baud rate divisor for sample clock=(system
clock/baud rate)/16.
 UART RECEIVER
It tests the state of incoming signal on each
clock pulse , looking for the beginning of the
start bit.
If the start bit lasts atleast one-half of the bit
time, it is valid and signals the start of new
character.
Otherwise it is ignored.
cont`d.
After waiting ,the state of a line is again
sampled and resultant level clocked into a
shift register.
Many UARTS have a small fifo buffer memory
between the receiver shift register and the
host system interface.
Functional Block Diagram
 FPGA
Field Programming Gate Array is popularly
known as FPGA.
This is mainly used for the implementation of
the digital logic in the systems.
First commercial FPGA is introduced in the
1984 by Xilinx which contains 64
CLBs(Configurable Logic Blocks) and 58 inputs
and outputs .
cont`d.
 The FPGA architecture consists of mainly 3
components
1. Programmable logic blocks
2. Programmable routing
3. I/O blocks
 Programmable logic blocks are used to
implement the logic functions , programmable
routing is used to interconnects and where as
I/O blocks for off-chips.
 These are Prefabricated silicon chips that can be
programmed electrically to implement any
digital design .
 But today FPGA contains nearly 3 million logic
blocks and 1K inputs and outputs.
Architecture of FPGA
 FPGA DESIGN ADVANTAGES

FPGA has many advantages . Some of the

advantages are
Faster time
No NRE( Non Recurring Expenses)
Simpler design cycle

cont`d.
More Predictable Project Cycle
Field Re programmability
Massively parallel data processing
Reusability
Long term maintenance
Performance
 SOFTWARE/HARDWARE
• Hardware required:
 FPGA
JTAG
• Software required:
XILINX ISE 11.1 TOOL
 Plan to work:

First two weeks of month

Write the Program for the implementation of
transmitter section operation in FPGA
Last two weeks of month
Run the program and observe the simulation
result
cont`d.
Next month
 Damp the program of transmitter and
receiver in the FPGA
After damping the program then we
interfaced the computer with FPGA and
allows the computer to talk with the FPGA (or)
vice versa
Next month
Interface the two systems with UART on FPGA
 REFERENCES

1.Alexander Barkalov LT; Logic Synthesis for FSMBased control

2. Barkalov AA, Titarenko LA, Efimenko KN;
Optimization of circuits of compositional
microprogram control units implemented on fpga.
3. Bomar BW; Implementation of microprogrammed
control in fpgas. Industrial Electronics, IEEE
Transactions on, 2002; 49(2): 415–422.
4. Digilent. Digilent Basys2 Spartan-3E FPGA Board.
5. HU Likun WQ; Uart-based reliable communication
6. Roth Jr. CH, John LK; Digital Systems Design
Using VHDL. Thomson-Engineering, 2007.
7. Tomasi W; Advanced electronic communication