I2C BUS

I2C Introduction
 The I2C is a two wire serial protocol.

 I2C components can be interfaced by using two lines. First

one is serial data (SDA) line and second is serial clock (SCL)
line. The design architecture consists of a master controller
and a slave device.

 The I2C component supports I2C Slave, Master, and Multi-

Master configurations. The master initiates all communication
on the I2C bus and supplies the clock for all slaved devices.

 The I2C component supports the standard mode with speeds

up to 1000 kbps.
I2C Master-Slave Architecture
I2C Frame Format
 I2C Working
I2C works on 2 signals as SCL and SDA

SCL - Serial Clock

SDA- Serial Data

The design architecture consists of a master controller and a slave.

The master generates the START condition when SCL is HIGH and
SDA is having a transition from HIGH to LOW.

Master also generates STOP condition when SCL is in HIGH and SDA
is having a transition from LOW to HIGH.

Beside these two functions master also transfers and receives data
to/from different slave devices
When SDA is having negedge and SCL is positive level triggered then we
have START signal and with every SCL clock a bit is transferred. Combining
up to eight bit the slave receives an address.

Then come the R/W signal means whether the slave has to read or write
from/to address. At the very moment after R/W bit the last bit known as
acknowledgement bit is sent.

Then the slave sends bit by bit data and finalizing by the acknowledge bit
and the process comes to a STOP.
Common I2C Operation Sequence
The design supports common I2C operations. The sequence of
each operation is described in this section.

Burst Read or Sequential Read after sending slave address :

 Master issues a START condition

 Master sends I2C slave address + one H bit (READ)
 Slave issues ACK to master if address matches
 Master receives READ data, and issues ACK for each
received byte
 Master stops the operation by issuing NACK after last read
byte, followed by a STOP condition.
Common I2C Operation Sequence
Burst Write or Sequential Write :

 Master issues a START condition

 Master sends I2C slave address + one L bit (WRITE)
 Slave issue ACK to master if address matches
 Master sends address to be written to
 Slave issue ACK to master
 Master sends data to the specified address, and slave issues
ACK for each byte of Write data
 Master stops the operation by issuing a STOP condition after
the slave’s ACK.
Applications

 Embedded microprocessor boards

 Consumer and professional audio/video
 Communication systems
 Cost-effective reliable automotive systems
 Home and automotive radio