Device Fab

CMOS Inverter
(and resistor)

In semiconductor devices an inverter means that an input voltage (where there are
two possibilities) will be inverted to give the output (opposite (also called inverted)
voltage to the input). Typical voltage are 0 Volts and 5 Volts. These often
correspond to logic ‘0’ and logic ‘1’.
 CMOS Inverter, Cross-section, Plan View

In the following slides we will

work through how this is
formed and operated

For those of you who would like to know more about CMOS, please go to the RMIT videos on this at
https://equella.rmit.edu.au/rmit/access/hierarchy.do?topic=c3e59c79-37b0-42a6-9fbf-a2a0ee7cfd3b&page=1
 CMOS Inverter, Cross-section with electrode definitions

Substrate contacts are critical to correct operation of CMOS Substrate must be tied to GND,
n-well to VDD (reverse-biased diodes isolate regions). Metal to lightly-doped semiconductor
forms poor connection called Schottky Diode – no good here . Must use heavily doped well
and substrate contacts. – Hence the extra p+ and n+ regions.
Select silicon
wafer
(low doping
concentration,
p-)

Form thick
oxide layer (for
masking
doping)

Deposit
photoresist
Use n-well
mask to UV
expose and
form
pattern in
photoresist

Wet etch
the oxide to
form
‘window’ to
silicon

Remove
remaining
photoresist
Do n-well
doping
using oxide
as pattern

Remove all
oxide

Grow high
quality
oxide for
use in MOS
part of
pMOS and
nMOS FETs.
Form Poly
An n-well is necessary to make a pMOSFET. An n-well is like a min n-type substrate
within an actual p-type substrate. This makes CMOS possible (The ‘C’ stands for
Complimentary – here meaning that both pMOS and nMOS are on the same Si chip
Repeat
pattern and
etch steps
for Poly
layer

Form thick
oxide layer
Pattern and
etch oxide for
nMOS
source/drain
regions and
n-well
contact

Do n+doping,

NOTE: at this stage, resistors

could also be formed by etching
Remove
oxide

Regrow
oxide and
repeat
process
steps to
form p+
regions of
pMOS and
substrate
contact
Etch oxide to form ‘windows’ to silicon where metal will contact silicon

Could make contact

‘openings’ to a
resistor too
 Deposit and pattern metal layer for CMOS Inverter

Cross-
section

Plan
view