Modeling Flash Memories

Modeling Flash Memories
for IC Designs
Luca Larcher
Università di Modena e Reggio Emilia

Reggio Emilia - Italy
luca.larcher@unimore.it
Luca Larcher Università degli Studi

September, the 14th di Modena e Reggio Emilia
Flash memories
 Flash memory market increased exponentially in the last
years
 Flash are pervasive in every modern electronic system

Floating-Gate (FG) transistor
 The FG transistor is the basic element of NOR and NAND
Flash memories
 The information bit is stored by transistor threshold voltage
(VT), which can be changed in a non-destructive way by
injecting/removing charge to/from FG
Control Gate
INTERPOLY OX.
Floating Gate
TUNNEL OX.
Drain
Source
P-substrate

NOR Flash array
 In a NOR array, a cell, i.e. Bitlines (BL)
a FG transistor is identified
by a WL – BL cross
Single NOR Flash

= FG MOSFET
G Wordlines (WL)
Sourcelines
S
D

NAND Flash array
Bitlines
 NAND Flash cells BSL

are organized in
strings
 Each string is
comprised of
16 Wordlines
32/64 cells,
Select Transistors
connected in
series
 High density, i.e.
high capacity is
thus achieved
GSL

Outline
 Motivations
 Floating Gate (FG) transistor model:
 DC model and FG voltage calculation
 Transient model
 Program/erase current
 Stress Induced Leakage Current, SILC
 NOR and NAND Flash Spice-like models
 Parameters and extraction procedure
 Simulation results
 Conclusions
Motivations
 Designing NAND and NOR Flash memories requires Spice-
like circuit simulations, that need accurate compact
models to be effective
 Flash memory cells are usually replaced with standard
MOS in industry circuit simulations
 FG potential is usually calculated through the capacitive
coupling coefficient method, i= Ci/CT
VFG  CG VCG  DVD  SVS  BVB
 Constant capacitive coupling coefficients leads to errors in
VFG calculation
 Optimum models should be: Spice-like, compact, accurate,
usable in DC and transient conditions
The FG transistor DC model
Control Gate
CPP
Floating Gate
VFG
Source Body Drain

P-substrate
CPP = interpoly dielectric capacitance

VFG = Floating Gate voltage
VFG calculation
CG
 VFG is calculated by solving
the charge neutrality
FG
VFG equation at the FG node:
D S QMOS + QCPP = QP/E

B
 QCPP = CPP(VFG-VCG)
 QP/E = charge injected into the FG during program/erase
(constant in DC conditions)
 QMOS = f(VFG,VS,VB,VD) is a the charge on the MOS gate, which is
a complex function of voltages, calculated by means of the MOS
model charge equations
Solution of charge equation
 The charge neutrality equation is an implicit equation in

VFG:
F(VFG) = QMOS(VFG) + QCPP(VFG) – QW/E = 0
 No analytical solution due to the complex QMOS expression

 Spice-like simulator solves it numerically through suitable
convergence algorithms
 F is monotonic versus VFG for all bias combinations
(VCG,VS,VB,VD), assuring the uniqueness, i.e. the physical
meaning of the derived VFG solution

The FG transistor transient model
 Current sources (IW1, IW2, IW3) are included to model
program and erase currents, i.e. Fowler-Nordheim (FN)
and Channel Hot Electron (CHE) currents
Control Gate
CPP
Floating Gate
Iw1 Iw3
VFG
Iw2
Source Drain
Body P-substrate
Fowler-Nordheim current sources
 Current sources analytically modeling Fowler/Nordheim
currents allow reproducing program-erase and erase
operations of NAND and NOR Flash memories,
respectively.
 BFN 
IFN Fox   A T A F  exp  
2
FN ox 
 Fox 
 AT = area of the tunneling region

 AFN , BFN = Fowler-Nordheim physical coefficients
depending on the Si/SiO2 barrier
 FOX = electric field across the tunnel oxide
FOX calculation
FOX 
 V
FG  VS,D,B   VFB  S  P
TOX
– VFB = flat-band voltage
– S = surface potential drop at Si/SiO2 interface
– P = surface potential drop at poly-Si/SiO2 interface
 To correctly evaluate S and P, poly depletion and

charge quantization effects are taken into account through
a self consistent model [1]
 The so calculated FOX has been included in the FG model
through empirical formulas
[1] L. Larcher et al., “A new model of gate capacitance …”, IEEE Trans. Elect. Devices
CHE current source
 CHE and Channel Initiated Secondary ELectron (CHISEL)
currents can be modeled through simplified approaches
allowing modeling the high energy distribution of hot carriers
[2]
Gate CHISEL
CHE
M4
e1 e1,2
Source e3 M2 M1 Drain
h2
Impact Ionization
M3
Body
h2,3
[2] L. Larcher, P.Pavan, “A New Analytical Model of Channel Hot Electron (CHE) and
CHannel Initiated Secondary ELectron (CHISEL) …,” MSM 2002, 2002, pp. 738-741.
Stress Induced Leakage Current, SILC
 SILC [3] is included through current sources allowing
simulating the threshold voltage degradation due to the aging
of the tunnel oxide induced by P/E cycles
 SILC modeled assuming the inelastic Phonon Trap-Assisted
Tunneling (PTAT) as conduction mechanism
cathode SiO2
Ep
xT
[3] L. Larcher et al., IEEE Trans. anode
Electr. Devices, Vol.48, N.2,
2001, pp.285-288.
tox
NOR Flash model & parameters
 The NOR Flash Spice-like model is the FG MOSFET model
 Parameters of M1 are extracted applying the standard
MOSFET parameter extraction procedure to the dummy cell,
that is a cell with FG and CG short-circuited
 Additional parameters
from SEM measurements
CG
and TCAD simulations :
FG-CG capacitance;
parameters of current FG
sources IW1 IW2
 Practically, no additional
costs compared to a S D
standard MOSFET M 1

NAND Flash model & parameters
 The NAND Flash memory string model is a sub-circuit
comprised of equivalent dummy cell MOSFETs, inter-poly
capacitances, coupling capacitances, P/E current sources
WL1 WL2 WLn
CFC CFC
CFS
BLm+1
WL1 WLn
SSL CFS CFFB CFFB CFS DSL
SL BLm
CFL
CFL
NAND Flash model & parameters -2
 Coupling capacitances between FGs of adjacent cells, FCF
and CFFB, are additional parameters derived from SEM
measurements and TCAD simulations
 Parameter of the equivalent MOSFET are extracted from
a string of dummy cells, paying attention to correctly
account for series resistance effects
 Again, current sources can be inserted to account for
program/erase Fowler-Nordheim currents
SSL WL1 WL15 WL32 DSL
SL BL

DC – NOR Flash: IDS-VCG
10-4
VSB (exp) 0..2 step 0.5V
10-5
10-6 VSB= 0V
W=0.25 mm
10-7 L=0.375 mm
I DS (A)
10-8 VSB= 2V
10-9
VDS= 0.1V
10-10
simulation
-11
10
2 3 4 5 6 7
VCG (V)
DC – NOR Flash: IDS-VDS
25
simulation VCG= 4 V
20 VB= 0 V
VCG= 3.75 V
I DS (mA)
15
VCG= 3.5 V
10
VCG= 3.25 V
5 VCG= 3 V
0
0 0.3 0.6 0.9 1.2 1.5 1.8
VDS (V)
DC – NOR Flash: IDS-VCG
60
simulation W=0.16 mm
50 L=0.3 mm
VD (exp)
40
0.1 V
I D (mA)
0.7 V
30 1.3 V
1.9 V
20
10
0
2 2.5 3 3.5 4 4.5 5 5.5 6
VCG (V)
DC - NAND Flash: IDS-VCG
1.0E-06
cell #16 in the string
VD=0.1V
1.0E-07
IDS [A]
1.0E-08
VB=0V
1.0E-09 VB=-1V
VB=-2V
SIM
1.0E-10
-1.0 0.0 1.0 2.0 3.0
VCG [V]
Erase – NOR Flash: VT - time
7 Erase bias:
VG0(exp) -2.7..-4.7 step 1V
D float
6
VS=VB=8 V
5
VG0= -4.7 V VCG
4
V T (V)
VG,MAX
3 VG0= -2.7 V
2
VG0
1 Time
simulation VB= VS= 8 V
0
0 0.1 0.2 0.3 0.4
Time (s)
Erase – NOR Flash: VT - time
7
dV/dt (exp)= 12.5,20,25,30,35,50,60 V/s
6 simulation
5
4
V T (V)
dV/dt= 12.5V/s
3
2
1
dV/dt= 60 V/s
0
0 0.1 0.2 0.3 0.4
Time (s)

Program – E2PROM Flash: VT
4
Lines: simulations
3 Symbols: measures
2
No free
parameter
VT (V)
1
0.3 0.4 0.5 0.6 to improve
0 TRISE(m 12V VCG-ramp the fitting
s)
-1 quality!!
-2 VD=VB=0V
TRISE VS=0V
-3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (ms)
Program – E2PROM Flash: tunnel current
60
excellent fitting using real VCG VVCG ramp
D-ramp
50 ramp!! Nominal
40
ITUN (pA)
Real
TRISE
30
20
10 Lines: simulations
Symbols: measures
0
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
Time (ms)
E2PROM Flash: retention simulation
NC NC = number
4.7 of P/E cycles
10 - 1 - fresh E2PROM cell
4.2 2 left unbiased in
10
retention
VT(V)
3.7
10
3 VT reduction
induced by
4
3.2 10 SILC, included
by some
NC= 105
2.7 current sources
0 1 2 3 4 5 6 7 8 9 10
Years
Advantages & conclusions
 This Flash memory modeling approach has several
advantages
 The parameter extraction procedure is simple
it is similar to the one of a standard MOSFET and few
additional parameters are derived from SEM measurements
and TCAD simulations
 The simulation time is comparable to MOSFET

 VFG calculation procedure does NOT use capacitive
coupling coefficients
the VFG calculation is much more accurate compared to the
usual method considering capacitive coupling coefficients as
constants, which introduces errors
Flash coupling coefficients: CG
VB=-1V CG
VS=0V 0.72
0.70
0.68
0.66
0.64
0
22.
11.13 0
33.38
55.63
44.5 1
9 8 66.75 2
3
4
VCG 5
VFG  CG VCG  DVD  SVS  BVB VD

Advantages & conclusions -2
 NOR and NAND Flash compact models are simply developed as
sub-circuit
 DC, transient and reliability simulations of single devices and
circuits excellently reproduce measurements without free
parameters to improve the fitting quality
 Easily scalable: scaling rules are taken into account in the
MOSFET model itself, and they do not affect the VFG calculation
 Easily upgradeable: voltage and current sources can be
replaced/modified independently
 Can be used for statistical analysis (effects of statistical
fluctuation of critical parameters, …)

References
o Paolo Pavan, Luca Larcher, Andrea Marmiroli, Floating Gate devices: Operation
and Compact Modeling, Kluwer Academic Publishers, 2004, 140 pp., ISBN 1-4020-
7731-9
 L. Larcher et al., Bias and W/L Dependence of Capacitive Coupling
Coefficients in Floating Gate Memory Cells, IEEE Trans. on Electron Devices,
Vol. 48(9), pp. 2081-2089, 2001.
 L. Larcher et al., A New Compact DC Model of Floating Gate Memory Cells
Without Capacitive Coupling Coefficients, IEEE Trans. on Electron Devices,
Vol.49(2), pp. 301-307, 2002.
 L. Larcher et al., A complete model of E2PROM memory cells for circuit
simulations, IEEE Trans. on CAD, Vol. 22(8), pp. 1072-1079, 2003.
 L. Larcher and P. Pavan, Statistical simulations for Flash memory reliability
analysis and prediction, IEEE Trans. on Electron Device, Vol. 51(10), pp. 1636-
1643, 2004.
 Luca Larcher et al., Modeling NAND Flash memories for circuit simulations, IEEE
SISPAD, 2007
 L. Larcher et al., Flash memories for SoC: an overview on system constraints and
technology issues, (invited paper) IEEE IWSoC2005, 2005.


Modeling Flash Memories

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Modeling Flash Memories

Università di Modena e Reggio Emilia

Luca Larcher Università degli Studi

Luca Larcher Università degli Studi

Luca Larcher Università degli Studi

Single NOR Flash

Luca Larcher Università degli Studi

 NAND Flash cells BSL

Luca Larcher Università degli Studi

Source Body Drain

CPP = interpoly dielectric capacitance

D S QMOS + QCPP = QP/E

 The charge neutrality equation is an implicit equation in

 No analytical solution due to the complex QMOS expression

Luca Larcher Università degli Studi

 AT = area of the tunneling region

 To correctly evaluate S and P, poly depletion and

Luca Larcher Università degli Studi

SSL WL1 WL15 WL32 DSL

Luca Larcher Università degli Studi

Luca Larcher Università degli Studi

 The simulation time is comparable to MOSFET

VFG  CG VCG  DVD  SVS  BVB VD

Luca Larcher Università degli Studi

Luca Larcher Università degli Studi

Luca Larcher Università degli Studi

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