Course: RME 201

Course Title: Microcontroller and programmable logic controller

Course sub-title: Registers and their functions, 8051
Department of Robotics and Mechatronics Engineering (RME)
University of Dhaka

Dr. Shamim Ahmed Deowan

E-mail: sadeowan@gmail.com
 Registers and their functions, 8051
8051 CPU registers:
A (Accumulator)
B
PSW (Program Status Word)
SP (Stack Pointer)
PC (Program Counter)
DPTR (Data Pointer)
 Registers and their functions, 8051
The 8051 contains 34 general purpose or
CPU registers: working registers. Two of these, registers A
and B, comprise the mathematical core of
the 8051 central processing unit (CPU). The
other 32 are arranged as part of internal
A
RAM in four banks, B0-B3, of eight registers
B
each, named R0-R7.
R0
DPTR DPH DPL
R1

R2 PC PC
R3

R4 Some 8051 16-bit Register

R5

R6

R7

Some 8-bit Registers

of the 8051
 Registers and their functions, 8051
A register (E0H):
The 8051 has an 8 bit A and in the instruction set it is referred as
“A”. The accumulator is used in all arithmetic and logical
operations and has direct connection to ALU. One of the
operands is stored in the accumulator. After the operation is
performed, the result is stored in the A. In multiplication
operations, one of the 8 bit operands is stored in “A” register.
 Registers and their functions, 8051
After the operation, it stores the lower byte of the result in “A”
register.
In division operation, it holds an 8 bit dividend and after the
operation, the quotient is stored in the accumulator. It is also
used in indexed addressing mode to access information from
program memory. “A” is bit addressable register.

B register (F0H):
The 8 bit “B” register is used during multiply and divide
operations. In multiplication operation, one of the 8 bit operands
is stored in “B” register. After the operation, it stores the higher
bytes of the results in “B” register. In division operation, it holds 8
bit divisor and after the operation the remainder is stored in “B”
register.
 Registers and their functions, 8051
For other functions, it can be used as 8 bit general purpose
register. “B” is bit addressable register.

Flags and program status word (D0H):

Flags are 1-bit registers provided to store the results of certain
program instructions. Other instructions can test the condition of
the flags and make decisions based upon the flag states. In order
that the flags may be conveniently addressed, they are grouped
inside the program status word (PSW) and the power control
(PCON) registers.
 Registers and their functions, 8051
The 8051 has four math flags that respond automatically to the
outcomes of math operations and three general-purpose user
flags that can be set to 1 or cleared to 0 by the programmer as
desired. The math flags include carry (C), auxiliary carry (AC),
overflow (OV), and parity (P). The user flags are named F0, GF0
and GF1; they are general-purpose flags that may be used by the
programmer to record some even in the program.

The program status word is shown below. The PSW contains the
math flags, user program flag F0 and the register select bits that
identify which of the four general-purpose register banks is
currently in use by the program.
CY AC F0 RS1 RS0 OV ………. P
Bit 7 Bit 0
 Registers and their functions, 8051
The Program Status Word special function
registers
Table: Bit addressable PSW.0 to PSW.7
 Registers and their functions, 8051
The Stack and stack pointer:
The stack refers to an area of internal RAM that is used in
conjunction with certain opcodes to store and retrieve data
quickly. The 8-bit stack (SP) register is used by the 8051 to hold
an internal RAM address that is called the “top of the stack”. The
address held in the SP register is the location in internal RAM
where the last byte of data was stored by a stack operation.

When data is to placed on the stack, the SP increments before

storing data on the stack so that the stack grows up as data is
stored. As data is retrieved from the stack, the byte is read from
the stack, and then the SP decrements to point to the next
available byte of stored data.
 Registers and their functions, 8051
The Stack and stack pointer:
pop
push

stack pointer

stack
 Registers and their functions, 8051
The Stack and stack pointer:
 Registers and their functions, 8051
Data pointer (DPH-83H and DPL-82 H):
The data pointer (DPTR) consists of two 8-bit registers- a high
byte (DPH) and a low byte (DPL). Its intended functions is to hold
a 16 bit address. It is used to furnish address information for
internal and external program memory and for external data
memory.

Program Counter:
Program counter (PC) is a 16 bit register. The 16 –bit program
counter specifies the address of the next instruction to be
executed. After reset, the PC will be set to 0000H and the CPU
will start executing the first instruction stored at the program
location 0000H. The 8051 fetches the instruction one byte at a
time and after fetching, it increments the PC by 1.
 Internal Memory
The 8051 has a Harvard architecture, which uses the same
address, in different memories, for code and data. Internal
circuitry accesses the correct memory based upon the nature of
the operation in progress.
Internal RAM
 On-ChipN.B.:Memory Byte

Internal
shown toRAM
addresses are
the left:
bit addresses
registers are
Fig.2: Internal RAM structure

shown inside a
location
 Register Banks

 Active bank selected by PSW [RS1,RS0] bit

 Permits fast “context switching” in interrupt
service routines (ISR).
 Register banks
1F

Bank 3
Four Register Banks
18
Each bank has R0-R7
17 Selectable by psw.2,3

Bank 2

10
0F

Bank 1

08
07 R7
06 R6
05 R5
04
03
R4
R3
Bank 0
02 R2
01 R1
00 R0
 Bit Addressable Memory
2F 7F 78 20h – 2Fh (16 locations X 8-bits =
2E 128 bits)
2D
2C Bit addressing:
2B mov C, 1Ah
2A or
29 mov C, 23h.2
28
27
26
25
1A
24
10
23
0F 08
22
07 06 05 04 03 02 01 00
21
20
 Bit Addressable RAM

Fig.3: Summary of the 8051 on-chip data memory (RAM)

 Special Function Registers

DATA registers

CONTROL registers
Timers
Serial ports
Interrupt system
Analog to Digital converter
Digital to Analog converter Addresses 80h – FFh
Etc.
Direct Addressing used to
access SPRs
 Bit Addressable RAM

Fig.4: Summary of the 8051 on-chip data memory (Special Function Registers)
 Internal ROM

The 8051 is organized so that data memory and program code

memory can be in two entirely different physical memory
entities. Each has the same address ranges.

A corresponding block of internal program code, contained in an

internal ROM, occupies code address space 0000h to oFFFh. The
PC is ordinarily used to address program code bytes from
addresses 0000h to FFFFh. Programm addresses higher than
0FFFh, which exceed the internal ROM capacity, will cause the
8051 to automatically fetch code bytes from external program
memory.