IMPLEMENTATION AND DESIGN OF

NEURON USING VHDL

Project Guide:
 AIM

 To design a neuron circuit and simulate the

behaviour of a biological neuron, how nervous
impulses called spikes are transmitted through
the body of the neuron ,from the dendrites to
axon.
 TOOLS USED

 XILINX
 MODELSIM SIMULATOR

 MULTISIM
INTRODUCTION OF THE NEURON
 An Artificial Neural Network (ANN) is an
information processing paradigm that is inspired
by the way biological nervous systems, such as
the brain process information.
 An artificial neuron is a device with many inputs
and one output.
 The neuron has two modes of operation; the
training mode and the using mode.
 Dendrites of a neuron are considered as inputs
and axon as the output.
THE NERVOUS SYSTEM
 The human nervous system can be broken down into three stages
that may be represented in block diagram form as:

The receptors collect information from the environment – e.g. photons on

the retina.
The effectors generate interactions with the environment – e.g. activate
muscles.
The flow of information/activation is represented by arrows – feed forward
and feedback.
Naturally, in this module we will be primarily concerned with the neural
network in the middle
KEY TERMINOLOGIES
 Axon: An axon or the nerve is a long splendid projection of a
nerve cell, or neuron that conducts electrical impulses away from
the neuron’s cell body.
 Dendrite: are the branched projections of a neuron that act to
conduct the electrical simulation received from other neural cells
to the cell body.
 Synapse: This is the contact site between the axon of the
first neuron & the dendrites of the next neurons.
Soma: The soma is the central unit of the neuron , it
receives signals from other neurons across the different
dendrites.
 What are Artificial Neural Networks used for?

Brain modelling : The scientific goal of building

models of how real brains work.
This can potentially help us understand the nature
of human intelligence, formulate better teaching
strategies, or better remedial actions for brain
damaged patients.
Artificial System Building : The engineering goal
of building efficient systems for real world
applications. This may make machines more powerful,
relieve humans of tedious tasks, and may even
improve upon human performance.
Our project Circuit of Neuron
 VHDL CODING OF MULTIPLEXER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux4 is
port (A1, A2 : in std_logic_vector (3 downto 0);
sel : in std_logic;
Y : out std_logic_vector (3 downto 0));
end mux4;
architecture Behavioral of mux4 is
begin
process (A1,A2,sel)
begin
if Sel = '0' then
Y <= A1 ;
else
y <= A2;
end if;
end process;
end Behavioral ;
 VHDL OF COUNTER MODULO-1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
port(clr,ce,oe,clk:in std_logic;
q:inout std_logic);

end counter;

architecture Behavioral of counter is

begin
process (clr,ce,oe,clk)
begin
if (clr='0') then
q <='0';
elsif (oe = '0')
then q <= '1';
elsif (ce = '1'and clk'event) then
q <= (not q);
else q <= '0';
end if;

end process;

end Behavioral;
MULTIPLIER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

package converter1 is
function btoi(a:in std_logic_vector(3 downto 0)) return integer;
procedure itob(a:in integer; b:out std_logic_vector(7 downto 0));
end package converter1;

package body converter1 is

function btoi(a:in std_logic_vector(3 downto 0)) return integer is
variable u,v: integer;
begin
u:=0; v:=1;
for i in 0 to 3 loop
if(a(i)='1') then
u:=u+v; end if;
v:=v*2; end loop;
return u;
end function btoi;
procedure itob(a:in integer; b:out std_logic_vector(7 downto 0)) is
variable v,u:integer;
variable x:std_logic_vector(7 downto 0);
begin
v:=a;
for i in 0 to 7 loop
u:=v rem 2;
if(u=1) then
x(i):='1'; else x(i):='0'; end if; v:=v/2;
end loop;
b:=x;
end procedure itob;
end package body converter1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.converter1.all;
entity mul is
port (a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(7 downto 0));
end mul;

architecture Behavioral of mul is

begin
process(a,b)
variable p,q,c:integer;
variable d:std_logic_vector(7 downto 0);
begin
c:=0;
p:=btoi(a);
q:=btoi(b);
c:=p*q;
itob(c,d);
s<=d;
end process;
end Behavioral;
 8-BIT REGISTER CODING

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rtg is
Port ( RIN : in std_logic_VECTOR(7 DOWNTO 0 );
EN_R : in std_logic;
ROUT : out std_logic_VECTOR(7 DOWNTO 0 ));
end rtg;
architecture Behavioral of rtg is

begin

PROCESS(RIN,EN_R)
BEGIN

IF(EN_R = '1') THEN ROUT <= RIN;

ELSE ROUT <="00000000";
END IF;
END PROCESS;

end Behavioral;
 FINITE STATE MACHINE

The current state of the machine is stored in the state memory, a

set of n flip-flops clocked by a single clock signal (hence
“synchronous” state machine).

 The state vector (also current state, or just state) is the value
currently stored by the state memory. The next state of the
machine is a function of the state vector and the inputs. Mealy
outputs are a function of the state vector and the inputs while
Moore outputs are a function of the state vector only.

CLK is the clock of the system. High RESET can stop everything
in finite state machine and START is the signal which allows the
neuron to begin its functioning after RESET is low.
VHDL CODING OF FINITE STATE MACHINE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fsma is
port(clk,reset,start,end_in:in std_logic ;
en_count,en_r,ce,clr,end_fsm:out std_logic);
end fsma;

architecture Behavioral of fsma is

begin
process(clk,reset,start,end_in)
variable a:std_logic_vector(2 downto 0);
variable i,j:integer:=0;
variable b: std_logic;
begin
process(clk,reset,start,end_in)
variable a:std_logic_vector(2 downto 0);
variable i,j:integer:=0;
variable b: std_logic;
begin
if(reset='1') then
a:="000";en_count<='0';
en_r<='0';
ce<='0';
clr<='0';
elsif (end_in = '1') then
clr<='1';en_r<='0';
ce<='0';
en_count<='0';

elsif(start='1' and clk'event ) then

if(j=0) then
a:="100" ;
j := j+1;
else
b:=a(0);
for i in 0 to 1 loop

a(i):= a(i+1);
end loop;

a(2) := b;
en_count<=a(2); en_r<=a(1);
ce<=a(0);
end if ;
else clr<='0';en_r<='0';
ce<='0';
en_count<='0';
end if;
end process;
end Behavioral;
 CODING OF 2’COMPLEMENT

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity compliment is
Port ( CIN : in std_logic_vector(7 DOWNTO
0 );
COUT : out std_logic_vector(7 DOWNTO
0 ));
end compliment;
architecture Behavioral of compliment is
begin
PROCESS(CIN)
VARIABLE V : std_logic_vector(7 DOWNTO 0 );
BEGIN

V:= NOT CIN ;

COUT<= v+ "00000001" ;

END PROCESS;
end Behavioral;
 ADDITION AND ACCUMULATION

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity add is
Port (B : in std_logic_vector(7 DOWNTO 0 );
clr,ce : in std_logic;
CO: out std_logic;
accu :inout std_logic_vector(7 downto
0));
end add;
architecture Behavioral of add is
begin
process(B,ce,clr)
variable Y:std_logic_vector(7 downto 0);
variable count : integer:=0;
begin
if (clr = '1') then
accu <="00000000" ;
elsif (ce = '1') then
accu <= B;

else accu<="11111111" ;
if((accu(7)='1' and B(7)='1')or((accu(7)='1' OR
B(7)='1')AND B(6)='1'AND accu(6)='1')) THEN
CO<='1';
else CO<='0';
end if;
end if;
end process;
end Behavioral;
 VHDL CODING OF ACTIVATION FUNCTION

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity acti is
port(a: std_logic_vector(7 downto 0);
sign : in std_logic;
output: out std_logic);
end acti;
architecture Behavioral of acti is

begin
process (sign,a)
begin
if (sign = '0') then
output <= '0';
elsif (sign = '1') then
if (a >= "10000000") then
output <= '1';
else output <= '0';

end if;
end if;
end process;

end Behavioral;
 INTERFACING
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PROJECTNEURON is
port (A1,A2: in std_logic_vector(3 downto 0);
W1,W2: in std_logic_vector(3 downto 0);
clk1,clr,oe,ce : in std_logic;
clk,reset,start,end_in :in std_logic;
SA1,SA2,SW1,SW2 :in std_logic;
output: out std_logic);
end PROJECTNEURON;
architecture Behavioral of PROJECTNEURON is

component add
port(B : in std_logic_vector(7 DOWNTO 0 );
ce,clr : in std_logic;
CO : out std_logic;
accu : inout std_logic_vector(7 downto 0));
end component;

component acti
port (a: std_logic_vector(7 downto 0);
sign : in std_logic;
output: out std_logic);
end component;
component compliment
port (CIN : in std_logic_vector(7 DOWNTO 0 );
COUT : out std_logic_vector(7 DOWNTO 0 ));
end component;

component mux2
port (A1, A2 : in std_logic;
sel : in std_logic;
Y : out std_logic);
end component;

component counter
port (ce,oe,clr:in std_logic;
clk : in std_logic;
q:inout std_logic);
end component;

component fsma
port (clk,reset,start,end_in:in std_logic;
en_count,en_r,ce,clr:out std_logic);
end component;
component mul
port (a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(7 downto 0));
end component;

component mux4
port (A1, A2 : in std_logic_vector(3 downto 0);
sel : in std_logic;
Y : out std_logic_vector (3 downto 0));
end component;

component rtg
Port ( RIN : in std_logic_vector(7 DOWNTO 0 );
EN_R : in std_logic;
ROUT : out std_logic_vector(7 DOWNTO 0 ));
end component;
component mux8
port (A1, A2 : in std_logic_vector (7 downto 0);
sel : in std_logic;
Y : out std_logic_vector (7 downto 0));
end component;

signal s1,s14,s13,s15 : std_logic;

signal s0,s2:std_logic_vector (3 downto 0);
signal s7,s8,s9,s10,s16:std_logic_vector(7 downto 0);
signal s3,s4,s5,s6,s11,s21,s12,s17,s18,s19,s20: std_logic;
begin

m0: fsma port map (clk,reset,start,end_in,s3,s4,s5,s6);

m1: counter port map (ce,oe,clr,clk,s1);
m2: mux4 port map (A1,A2,s1,s0);
m3: mux4 port map(W1,W2,s1,s2);
m4: mul port map(s0,s2,s8);
m5: rtg port map(s8,s4,s7);
m6: compliment port map(s7,s9);
s14<=SA1 xor SW1;
s15<=SA2 xor SW2;
m7: mux2 port map(s14,s15,s1,s12);
s13 <= s12 and s4;
m8: mux8 port map(s7,s9,s13,s10);
m9: add port map(s10,s5,s6,s11,s16);
s17<=s14 and s15;
s21<=not s11;
s18<=s14 and s21;
s19<= s15 and s21;
s20<=s17 or s18 or s19;
m10:acti port map (s16,s20,output);
end Behavioral;
ADVANTAGES OF NEURAL NETWORK

 Adaptive learning: An ability to learn how to do tasks based on

the data given for training or initial experience.
 Self-Organisation: An ANN can create its own organisation or
representation of the information it receives during learning
time.
 Real Time Operation: ANN computations may be carried out in
parallel, and special hardware devices are being designed and
manufactured which take advantage of this capability.
 Fault Tolerance via Redundant Information Coding: Partial
destruction of a network leads to the corresponding degradation
of performance. However, some network capabilities may be
retained even with major network damage.
APPLICATIONS

 Used in medicines

 Modelling and Diagnosing the Cardiovascular

System

 Electronic noses

 Instant Physician

 Neural Networks in business

THANK YOU