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Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross
section. Typically L = 1 to 10 m, W = 2 to 500 m, and the thickness of the oxide layer is in the
range of 0.02 to 0.1 m.
Field-Effect Transistors (FETs)
Field-Effect Transistors (FETs)
Recent trend: more and more analog circuits are implemented in MOS technology for
lower cost integration with digital circuits in a same chip
Field-Effect Transistors (FETs)
Device Structure
v DSsat v GS V t
The drain current iD versus the drain-to-source voltage vDS for an enhancement-type
NMOS transistor operated with vGS > Vt.
Field-Effect Transistors (FETs) - Enhancement Type
The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate.
Field-Effect Transistors (FETs) - Enhancement Type
An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a
conductance whose value is determined by vGS. Specifically, the channel conductance
is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS. Note that the
depletion region is not shown (for simplicity).
Field-Effect Transistors (FETs) - Enhancement Type
Exercise 5.1
Field-Effect Transistors (FETs) - Enhancement Type
Exercise 5.1
v DS 0.2 iD 0.0004 Vt 1 v GS Vt 4
iD 4 A
K K 5 10
vGS Vt vDS 2
V
v DS
rDS rDS 500
iD
Field-Effect Transistors (FETs) - Enhancement Type
Derivation of ID- vDS Relationship
Derivation of ID- vDS Relationship
Field-Effect Transistors (FETs) - Enhancement Type
Cross section of a CMOS integrated circuit. Note that the PMOS transistor is
formed in a separate n-type region, known as an n well. Another arrangement is
also possible in which an n-type body is used and the n device is formed in a p
well.
Field-Effect Transistors (FETs)
Enhancement Type
(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with
the normal directions of current flow indicated. (b) The iD - vDS characteristics for
a device with Vt = 1 V and k’n(W/L) = 0.5 mA/V2.
Field-Effect Transistors (FETs)
Enhancement Type
Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly
away from the drain, thus reducing the effective channel length (by L).
Field-Effect Transistors (FETs)
Enhancement Type
iD
1
2
k' n
W
L
v GS V t 1 v DS
2
b)
nCox 20
1 W 2
iD nCox ( vGS Vt) iD 100
2 L
c)
1 W 2
iD nCox ( vGS Vt) iD 100
2 L
Exercise 5-5
1 W 2
iD nCox ( vGS Vt )
2 L
W
nCox 2 1
L
1 W 2
iD nCox ( vGS Vt )
2 L
1 2
iD 2 ( vGS Vt ) iD 4
2
W
iD kn [ ( vGS Vt ) vDS]
L
vDS
rDS
iD
1
rDS rDS 0.25 K
[ 2 ( ( vGS Vt ) ) ]
Field-Effect Transistors (FETs)
Depletion Type
The current-voltage
characteristics of a
depletion-type n-
channel MOSFET
for which Vt = -4 V
and k’n(W/L) = 2
mA/V2
Field-Effect Transistors (FETs)
Depletion Type
Field-Effect Transistors (FETs)
Depletion Type
MOSFET Circuits at DC
MOSFET Circuits at DC
MOSFET Circuits at DC
MOSFET Circuits at DC
MOSFET As An Amplifier
MOSFET As An Amplifier
MOSFET As An Amplifier
MOSFET As An Amplifier
MOSFET As An Amplifier – Small-Signal Analysis
MOSFET As An Amplifier – Small-Signal Analysis
MOSFET As An Amplifier – The T Equivalent Circuit Models
MOSFET As An Amplifier – Modeling the Body Effect
MOSFET As An Amplifier – Exercise 5.17
MOSFET As An Amplifier – Exercise 5.18
MOSFET As An Amplifier – Exercise 5.19-20
Biasing a MOS Amplifier In Discrete Circuits
Biasing a MOS Amplifier In Integrated Circuits
Biasing a MOS Amplifier In Integrated Circuits
Biasing a MOS Amplifier In Integrated Circuits
Biasing a MOS Amplifier In Integrated Circuits
Basic Configurations of Single-Stage IC MOS Amplifiers
Basic Configurations of Single-Stage IC MOS Amplifiers
Basic Configurations of Single-Stage IC MOS Amplifiers
Basic Configurations of Single-Stage IC MOS Amplifiers
Basic Configurations of Single-Stage IC MOS Amplifiers
Basic Configurations of Single-Stage IC MOS Amplifiers
Exercises 5.22, 5.23, 5.25, 5.26, 5.27, 5.28.
The CMOS Digital Inverter
The CMOS Digital Inverter
The CMOS Digital Inverter
The CMOS Digital Inverter
The CMOS Digital Inverter
MOSFET As An Analog Switch
The MOSFET Internal Capacitances and High-Frequency Model
The Junction Field-Effect Transistor (JFET)
Gallium Arsenide (GaAs) Devices - MESFET
The Spice Model and Simulation Examples
Exercise - 5.22
W
kn 0.5 Vt 2 RG 1000000 ID 0.001
L
VGS 10
given
1
1
2
0.5 VGS 2 2
Find VGS 4
VG 0 VS 4
4 ( 10) 3
RS RS 6 10
ID
10 0 4
VD 0 Thus RD RD 1 10
ID
Fig. 5.31 Conceptual circuit utilized to study the operation of the MOSFET as an amplifier.
Small-signal operation of the enhancement MOSFET amplifier.
Fig. 5.33 Total instantaneous voltages vGS and vD for the circuit in Fig. 5.31.
Fig. 5.34 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (channel-length modulation
effect); and (b) including the effect of channel-length modulation modeled by output resistance ro = |VA|/ID.
g mb gm
2 2 f VSB
Fig. 5.37 the T model of the MOSFET augmented with the drain-to-source resistance ro.
Fig. 5.41 Basic MOSFET current mirror.
V O V A2
Ro r o2
I O IO
Fig. 5.42 Output characteristic of the current source in Fig. 5.40 and the current mirror of Fig. 5.41 for the case Q2 is matched to Q1.
Fig. 5.45 The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q2; (c) graphical construction to
determine the transfer characteristic; and transfer characteristic.
Fig. 5.47 The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit
in (b).
Fig. 5.48 The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.
Fig. 5.52 (a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer
characteristic.
Fig. 5.53 The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer characteristic; and
(c) transfer characteristic.
Fig. 5.54 Small-signal equivalent circuit of the depletion-load amplifier of Fig. 5.43 (a), incorporating the body effect of Q2.
Fig. 5.55 (a) The CMOS inverter. (b) Simplified circuit schematic for the inverter.
Fig. 5.56 Operation of the CMOS inverter when v1 is high: (a) circuit with v1 = VDD (logic-1 level, or VOH); (b) graphical construction
to determine the operating point; and (c) equivalent circuit.
Fig. 5.57 Operation of the CMOS inverter when v1 is low: (a) circuit with v1 = 0V (logic-0 level, or VOL); (b) graphical construction to
determine the operating point; and (c) equivalent circuit.
Fig. 5.58 The voltage transfer characteristic of the CMOS inverter.
Fig. 5.59 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the
operating point as the input goes high and C discharges through the QN; (d) equivalent circuit during the capacitor discharge.
Fig. 5.64 The CMOS transmission gate.
Fig. 5.65 Equivalent circuits for visualizing the operation of the transmission gate in the closed (on) position: (a) vA is positive; (b) vA
is negative.
Fig. 5.67 (a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is connected
to the substrate (body); (c) the equivalent circuit model of (b) with Cdb neglected (to simplify analysis).
Fig. 5.68 Determining the short-circuit current gain Io/Ii.