VLSI Design &

Technology
UNIT I: HDL Design
Contents of Unit 1:
Data Objects
Data Types
Entity
Architecture
Modeling Styles
Sequential statements
Concurrent statements
Packages
Subprograms
Attributes
VHDL Test bench
Test benches using text files
VHDL modeling of combinational, sequential logics
FSM
Introduction to VHDL
Hardware Description Language
Stands for VHSIC Hardware
Description Language
VHSIC- Very High Speed Integrated
Circuits
VHDL is a IEEE standard
It is standard, technology/vendor
independent language
Applications are FPGA, CPLD &
ASIC programming
DATA OBJECTS
Signal
Variable
Constant
SIGNAL
Represents interconnection wires
Declared in
1. Entity declaration (referenced
by any architecture for that
entity)
2. Architecture declaration
(referenced by that architecture
only)
3. Package declaration (Global)
SIGNAL
Syntax:

SIGNAL signal _ name: signal_ type

[:=intial_value];

e.g:

SIGNAL X: bit:=‘1’;
VARIABLE
Used for local storage
Declared in
1. Process (referenced by that
process only)
2. Subprograms
VARIABLE
SYNTAX:

VARIABLE variable_name:
variable_type [:=value]
e.g:
VARIABLE Y: std_logic:=‘0’;
CONSTANT
Used for specific values
Declared in
1. Entity declaration (referenced
by any architecture for that
entity)
2. Architecture declaration
(referenced by that architecture
only)
3. Package declaration (Global)
CONSTANT
Syntax:

CONSTANT constant _ name:

constant_ type [:=intial_value];

e.g:

CONSTANT pi: real:=3.1414;

SIGNAL V/S VARIABLE
Variables more efficient as
assignments happen immediately
while signals scheduled to occur
Variables take less memory while
signals need more as more
information for scheduling and
signal attributes.
DATA TYPES
Pre-defined
1. Bit
2. Std_logic
3. Std_ulogic
4. Boolean
5. Integer
6. Natural
7. Real
8. Signed & Unsigned

User-defined
1. Integer
2. Enumerated
Pre-defined:
BIT & BIT_VECTOR

2 level logic
e.g:
Signal y:bit:=‘1’;
signal x:bit_vector(3 downto 0);
x<=“1101”;
“<=“ - used for assigning value to
a signal
“:=“- used for assigning value
to a variable
STD_LOGIC & STD_LOGIC_VECTOR

8 valued logic system

1. ‘X’ – Forcing Unknown
2. ‘0’ – Forcing Low
3. ‘1’- Forcing High
4. ‘Z’- High Impedance
5. ‘W’- Weak Unknown
6. ‘L’- Weak Low
7. ‘H’- Weak High
8. ‘-’ – Don’t Care
STD_LOGIC &
STD_LOGIC_VECTOR
Most of the levels are for simulation only.
‘0’,’1’,’Z’ are synthesizable
If 2 std_logic signals are connected to
the same node, then conflicting logic
levels are automatically resolved.
e.g:
Signal x:std_logic;
Variable y:std_logic_vector(0 to 3);
x<=‘0’;
y:=“0111”;
STD_ULOGIC &
STD_ULOGIC_VECTOR
9 level logic system
Along with 8 logic values in
std_logic, this has one extra logic
value ‘U’- Uninitialized.
Std_logic is a sub-type of
std_ulogic.
Conflicting logic levels are not
automatically resolved.
OTHERS
Boolean: True, False
Integer: 32 bit numbers
(-2,147,483,647 to
+2,147,483,647)
Natural: Non-negative integers
(0 to +2,147,483,647)
Real: numbers ranging from
-1.0E38 to +1.0E38 – not
synthesizable
OTHERS
e.g:
Ifready then ….. Boolean,
executed if ready is true
X<=-2244; Integer
Y<=100;
Integer/Natural
Z<=1.234 Real
Packages/libraries
Package std of library std – defines Bit,
Boolean, Integer and Real data types
Package std_logic_1164 of library
ieee – defines std_logic and std_ulogic
data types
Package std_logic_arith of library ieee –
defines signed and un-signed data
types and also data conversion
functions like conv_integer,
conv_unsigned etc.
User Defined:
Integer
Type my_integer is range 0 to
100;
A user defined sub-type of
integer
e.g:
Signal x: my_integer;
x<=23;
User Defined:
Enumerated
An enumerated data type typical
of a FSM
e.g:
Type state is st0,st1,st2,st3,st4;
signal next_state: state;
Encoding is sequential and
automatic unless specified by
user defined attribute.
ARRAYS
1D array – predefined in VHDL
Std_logic_vector, bit_vector

e.g:
signal x:std_logic_vector(3 downto 0):=“1111”;
2D array – user defined
Syntax:
type type_name is array (specification) of
data_type;
e.g:
Type matrix is array(0 to 3) of
std_logic_vector(7 downto 0);
signal x: matrix;
VHDL CODE
Contains:
Library declarations- 2 lines:
name of library, use clause
Entity- list of all input, output
ports
Architecture- description of how
the circuit behaves- 2 parts :
declarative part where constants
and signals are declared, code
part
e.g:
Library ieee;
Use ieee.std_logic_1164.all; ---- specifies multi-level logic like when std_logic data type used

Library std; ---- resource library (data types etc)

Use std.standard.all;
Library work;
Use work.all; ---- files are stored .vhd, all files created by complier, simulator

Entity new is
Port (a, b, c, clk : in bit;
D: out bit);
End new;
Architecture circuit of new is
Signal t:bit;
Begin
Process (clk)
Begin
If(clk’ event and clk=‘1’) then
T<=a and b;
D<=t or c;
End if;
End process;
End circuit;
MODELING STYLES
Three types:
1. Concurrent or data flow
Intermediate level of abstraction – working of
the system described in terms of data transfer
between registers
2. Sequential or Behavioral
describes circuit or system at a high level of
abstraction – only overall behavior specified
3. Structural
low level of abstraction - components used
and structure of the interconnection between
components specified
CONCURRENT STYLE
Entity add is
port (a, b: in std_logic;
sum, carry: out std_logic);
End add;
Architecture add1of add is
begin
sum<= a xor b;
carry<= a and b;
End add1;
------------------------------------------------------------------
entity mux is
port (a, b, c, d: in std_logic; sel : in std_logic_vector(1
downto 0); y: out std_logic);
end mux;
CONCURRENT STATEMENTS
When – 2 forms:
1. when/else
2. with/select/when
When/else
architecture muxa of mux is
begin
y<=a when sel=“00” else
b when sel=“01” else
c when sel=“10” else
d;
end muxa;
With/select/when
architecture muxb of mux is
begin
with sel select
y<=a when “00”
b when “01”
c when “10”
d when others;
end muxb;
CONCURRENT STATEMENTS
Generate – allows a section of code to
be repeated.
typical – for generate
e.g – shift register
Block- 1. Simple block, 2. Guarded block
1. Simple block- used for partitioning of
code, so code is more readable,
manageable
2. Guarded block- guard expression
(Boolean expression), guarded
statement
GUARDED BLOCK
Architecture dff1 of dff is
begin
b1: block(clk’ event and clk=‘1’) --- guard
expression

begin
q<=guarded d; ---- guarded statement

end block b1;

end dff1;

Equivalent to a process statement.

SEQUENTIAL STATEMENTS
Statements inside Process,
Function, Procedure – sequential
Process, Function, Procedure –
concurrent
Variables allowed
Statements allowed: If, Wait,
Case, Loop
PROCESS –Sequential logic
Architecture dff1 of dff is
begin
process(clk, rst)
begin
if (rst = ‘1’) then
q<=‘0’;
elsif (clk’event and clk=‘1’) then
q<=d;
end if;
end process;
end dff1;
PROCESS – Combinational logic
architecture mux1 of mux is
begin
process(sel, a, b, c, d)
begin
case sel is
when “00” => y<=a;
when “01” => y<=b;
when “10” => y<=c;
when “11” => y<=d;
when others => NULL;
end case;
end process;
end mux1;
PROCESS - LOOP
entity fora is
port( a: in bit; o: out bit_vector (0 to 7));
end for a;
architecture behave of fora is
begin
process (a)
begin
for i in 0 to 7 loop
o(i)<=‘1’;
end loop;
end process;
end behave;
PROCESS - LOOP
process (a)
begin
for i in 0 to 7 loop
if (a=‘0’) then
exit; -----/next
else
o(i)<=‘1’;
end if;
end loop;
end process;
PROCESS - LOOP
process (a)
variable i : integer range 0 to 7;
begin
while(i<=7) loop
o(i)<=‘1’;
end loop;
end process;
PROCESS - WAIT
Wait:
1. Wait until
2. Wait for ---- Not synthesizable
used for simulation
only
e.g wait for 10ns;
3. Wait on
No sensitivity list
PROCESS - WAIT
Architecture dff1 of dff is
process
begin
wait until (clk’event and clk=‘1’);
if (rst = ‘1’) then
q<=‘0’;
else
q<=d;
end if;
end process;
end dff1;
PROCESS - WAIT
Process
begin
wait on clk, rst;
if(rst=‘1’) then
q<=‘0’;
elsif (clk’event and clk=‘1’) then
q<=d;
end if;
end process;
STRUCTURAL STYLE
Low level of abstraction
Entity described as set of
interconnected components
e.g: Half Adder
STRUCTURAL STYLE
architecture add1 of add is
component xor1 is
port (x, y: in bit; z: out bit);
end component; ----component declaration

component and1 is
port (l, m: in bit; n: out bit);
end component;
begin
x1: xor1 port map (a, b, sum);----component
instantiation

x2: and1 port map (a, b, carry);

end add1;
SUBPROGRAMS
Functions
Procedures
Sequential code like process
All statements inside process are
allowed
Intended for library allocation,
can be used in programs
Purpose – code reuse, sharing
FUNCTIONS
Computes single value
All parameters are input
parameters or signal parameter
Return statement returns value
to the calling program
Uses - resolution function, type
conversion function
FUNCTION
entity adder is
Port (x, y: in bit; carry, sum : out bit);
end adder;
architecture add1 of adder is
function add_bits (a, b:bit) return bit is
variable result : bit;
result : a xor b;
return result;
end add_bits;
begin
carry<= add_bits(x, y); ----- call to function
sum<= x and y;
end add1;
FUNCTION
architecture dff1 of dff is
function rising_edge (signal s:std_logic) return Boolean is
begin
if (s’event and s=‘1’) then
return true;
else
return false;
end if;
end rising_edge;
begin
process (clk)
begin
if rising_edge (clk) then
q<=d;
end if;
end process;
end dff1;
PROCEDURE
Returns zero or more than one
value
Can have input parameters,
output parameters and in-out
parameters
Procedure call is statement of its
own
Procedure argument list has
direction associated with each
parameter
PROCEDURE
architecture arch of min_max is
procedure sort (signal in1,in2:in integer range 0 to 255;
signal min, max: out integer range 0 to 255) is
begin
if (in1>in2) then
max<=in1; min<=in2;
else
max<=in2; min<=in1;
end if;
end sort;
begin
process (ena)
begin
if (ena =‘1’) then sort (i1, i2, min_o, max_o);
end if;
end process;
end arch;
PACKAGES
Contain user defined data types,
constants, components, functions,
procedures
Allows code sharing, partitioning,
reuse
Two parts:
1. Package declaration (Mandatory)
2. Package body (required when
subprograms declared in
package declaration)
PACKAGE
Package declaration:

library ieee;
use ieee.std_logic_1164.all;

package my_package is
type state is (st1,st2,st3,st4);
constant vec : std_logic_vector(7 downto 0);
component xor1 is
port (x, y: in bit; z: out bit);
end component;
end my_package;
PACKAGE
package my_package1 is
component xor1 is
port (x, y: in bit; z: out bit);
end component;
function rising_edge (signal s:std_logic) return
Boolean;
end my_package1;
package body my_package1 is
function rising_edge (signal s:std_logic) return
Boolean is
begin
return (s’event and s=‘1’)
end rising_edge;
end my_package1;
PACKAGE
Library ieee;
Use ieee.std_logic_1164.all;
Use work.my_package1.all;

entity add is
port(a, b: in bit; sum, carry: out bit);
end add;
architecture add1 of add is
begin
x1: xor1 port map (a, b, sum);
carry<= a and b;
end add1;
PACKAGE
Library ieee;
Use ieee.std_logic_1164.all;
Use work.my_package1.all;

entity dff is
port( d, clk : in bit; q: out bit);
end dff;
architecture dff1 of dff is
begin
process (clk)
begin
if rising_edge (clk) then
q<=d;
end if;
end process;
end dff1;
ATTRIBUTES
Five classes of predefined attributes:
1. Value attributes: returns a constant
value
2. Function attributes: calls a function
that returns a value
3. Signal attributes: creates a new
signal
4. Type attributes: returns a type
name
5. Range attributes: return a range
ATTRIBUTES- Value Kind
Attributes specified by character “’”
and then attribute name. Object
preceding ‘ is the object that the
attribute is attached to.
1. T’left: returns left bound of type or
subtype
2. T’right: returns right bound of type or
subtype
3. T’high: returns upper bound of type
or subtype
4. T’low: returns lower bound of type or
subtype
ATTRIBUTES: Value kind
e.g:
Architecture arch of b is
type color is (blue, green, yellow, red);
signal color1, color2, color3, color4:color;
begin
color1<=color’left; ----returns blue
color2<= color’right; ----returns red
color3<=color’high; ----returns red
color4<=color’low; ----returns blue
end arch;
ATTRIBUTES: Value kind
Type bit4 is array(0 to 3) of bit;
Variable len : integer;
Len:= bit4’length; ----returns 4
ATTRIBUTES: Function
kind
A function call occurs that uses
the value of the input argument
to return a value. Three types:
1. Function type attributes: return
type value
2. Function array attribute: return
array bound
3. Function signal attributes: return
signal history information
ATTRIBUTES: Function
type
1. T’pos(value) – returns position number of
value passed in
2. T’val (value) – returns value from position
number passed in
3. T’succ (value) – returns next value in type
after input value
4. T’pred (value) – returns previous value in
type after input value
5. T’leftof (value) – returns value
immediately to the left of the input value
6. T’rightof (value) – returns value
immediately to the right of the input value
ATTRIBUTES: Function
type
e.g:
type color is (red, yellow, green, blue,
purple, orange);
signal color1: color;
color1’pos(red) -----returns 0
color1’val(2) ------returns green
color1’succ(blue) ----returns purple
color1’pred (blue) ----returns green
color1’rightof (blue) ----returns purple
color1’leftof (blue) ----returns green
ATTRIBUTES: Function signal
Used to return information about the
behavior of the signals
1. s’event – returns true if event occurred
during current delta
2. s’active - returns true if transaction
occurred during current delta
3. s’last_event – returns time elapsed since
last event on signal
4. s’last_value – returns value of s before last
event
5. s’last_active – returns time elapsed since
the last time signal was active
ATTRIBUTE - USER DEFINED
type color is (red, green, blue,
white);
- Encoding is binary by default
To change encoding, user
defined attribute is used:

Attribute enum of color: type is “11

00 10 01”;
FINITE STATE MACHINES
Any sequential circuit is a finite
state machine as behavior of any
sequential can be represented
using finite no. of states.
Two types:
1. Moore type – output depends
only on present state of the circuit
2. Mealy type – output depends on
present state as well as primary
inputs of the circuit
FINITE STATE MACHINES
State Machine Diagram

Combinational
Input output
Circuit

 Next
State
Present Sequential
Circuit
State

Clock Reset
FINITE STATE MACHINES
 Generalized code for lower section- Sequential
Circuit:

process(clk, rst)
begin
if (rst = ‘1’) then
present_state<=st0;
elsif (clk’event and clk=‘1’) then
present_state<=next_state;
end if;
end process;
FINITE STATE MACHINES
Generalized code for upper section- combinational circuit:
process (input, present_state)
begin
case present_state is
when state0 =>
if (input = ----) then
output<=value1;
next_state<=state1;
else -----
end if;
when state1 =>
if (input = ----) then
output<=value1;
next_state<=state2;
else -----
end if;
-------
end case;
end process;
FINITE STATE MACHINES
e.g: Moore type
rst
d=1
State d=1 State
A B
(x=a) (x=b)

d=0 d=0
FINITE STATE MACHINES Design
Template 1
VHDL Code

entity fsm is
port (a, b, d, clk, rst: in bit; x: out bit);
end fsm;
architecture fsm1 of fsm is
type state is (stateA, stateB);
signal prs_state, nxt_state: state;
begin
----lower section------
process(clk, rst)
begin
if (rst = ‘1’) then
prs_state<=stateA;
elsif (clk’event and clk=‘1’) then
prs_state<=nxt_state;
end if;
end process;
FINITE STATE MACHINES
------Upper section -------------
process (input, prs_state)
begin
case prs_state is
when stateA =>
x<=a;
if (d=‘1’) then
nxt_state<=stateB;
else nxt_state<=stateA;
end if;
when stateB =>
x<=b;
if (d=‘1’) then
nxt_state<=stateA;
else nxt_state<=stateB;
end if;
end case;
end process;
end fsm1;
FINITE STATE MACHINES Design
Template 2
entity fsm is
port (a, b, d, clk, rst: in bit; x: out bit);
end fsm;
architecture fsm1 of fsm is
type state is (stateA, stateB);
signal prs_state, nxt_state: state;
signal temp: bit;
begin
----lower section------
process(clk, rst)
begin
if (rst = ‘1’) then
prs_state<=stateA;
elsif (clk’event and clk=‘1’) then
prs_state<=nxt_state;
x<=temp;
end if;
end process;
FINITE STATE MACHINES
------Upper section -------------
process (input, prs_state)
begin
case prs_state is
when stateA =>
if (d=‘1’) then
nxt_state<=stateB; temp<=a;
else nxt_state<=stateA; temp<=b;
end if;
when stateB =>
temp<=b;
if (d=‘1’) then
nxt_state<=stateA; temp<=b;
else nxt_state<=stateB; temp<=a;
end if;
end case;
end process;
end fsm1;
TEST BENCH
Used to verify the functionality of
a design
The test bench instantiates the
Design Under Test (DUT)
The test bench provides
necessary inputs to the DUT and
examines the output from DUT
VHDL provides the capability of
writing test bench in the same
language
TEST BENCH

TEST BENCH
TESTER DUT
TEST BENCH
entity dff is
port (d, clk, rst: in bit; q: out bit);
end dff;
------Test bench-------
entity testbench is
end testbench;
architecture behave of testbench is
component dff is
port (d, clk, rst: in bit; q: out bit);
end component;
signal d, clk, rst, q : bit;
TEST BENCH
begin
u1: dff port map (d=>d, clk=>clk, rst=>rst, q=>q);
ta: process
begin
rst<=‘1’;
wait for 10ns;
rst<=‘0’;
d<=‘1’;
wait for 50ns;
d<=‘0’;
wait for 50ns;
end process;
tb: process
begin
clk<=‘1’;
Wait for 10ns;
clk<=‘0;
wait for 10ns;
end process;
End behave;
TEST BENCH
entity mux is
port (in: in std_logic_vector (3 downto 0); sel: in
std_logic_vector(1 downto 0); y:out std_logic);
end mux;
------Test bench--------
entity testmux is
end tetsmux;
architecture behave of mux is
component mux is
port (in: in std_logic_vector (3 downto 0); sel: in
std_logic_vector(1 downto 0); y:out std_logic);
end component;
signal in: std_logic_vector (3 downto 0);
signal sel: std_logic_vector(1 downto 0);
signal y: std_logic;
TEST BENCH
begin
u1: mux port map(in=>in, sel=>sel, y=>y);
tb: process
begin
sel<=“00”;
in<=“0001”;
wait for 100ns;
sel<=“01”;
in<=“0010”;
wait for 100ns;
sel<=“10”;
in<=“0100”;
sel<=“11”;
in<=“1000”;
end process;
end behave;
TEST BENCH USING TEXT FILE
Dumping results into a text file:
The values of signals at specific times
can be written into a text file using
WRITE procedures provided in the
predefined TEXTIO package.
Reading vectors from a text file:
Using READ procedures provided in the
predefined TEXTIO package, reading
stimulus from a text file is possible.
• Refer to page nos- 271 – 280 of T3
METASTABILITY
 Itis the state of the circuit which is neither
‘0’ nor ‘1’
 As a result circuit acts in unpredictable way
and may lead to system failure
 Metastable states are avoidable in fully
synchronous systems when input set up and
hold times of flip flop are completely satisfied
But for asynchronous inputs connected to flip
flops, the set up and hold time
A circuit in metastable state eventually
settles in one of the stable states but the
time required to recover is not predictable
METASTABILITY
Waveforms
METASTABILITY
Synchronizer
REFERENCES
Reference Book:
1.Charles Roth, “Digital System
Design using VHDL”, Cengage
Learning
Text Book:
1. Douglas Perry, “VHDL”, McGraw Hill
2. Volnei Pedroni, “Circuit Design with
VHDL” , PHI
3. J. Bhasker, “A VHDL Primer”,
Pearson Education
TOPIC WISE REFERENCES
Data Objects – T1,T2
Data Types – T1, T2
Entity - T2, R1
Architecture – T2
Modeling Styles – T2, R1
Sequential statements – T1, T2, R1
Concurrent statements - T1, T2, R1
Packages – T1, T2
Subprograms – T1, T2
Attributes – T1, T3
VHDL Test bench – T3
VHDL modeling of combinational, sequential logics –
T1,T2,R1
FSM – T2
Metastability - Internet