Improving Op Amp performance

• Improving gain
– cascoding
– cascading
– feedback
– feed forward
– push pull
– complementary input
– decreasing current
– using “analog friendly” CMOS processes
– using bipolar
• Improving speed
– Increasing UGF,  increase transient speed
• Settling may not improve, which depends on PM and
secondary poles
• Cannot simply increase W/L ratio  optimal sizing for a
given CL
• Two stage optimal design: can potentially achieve higher
UGF than single stage
– Increasing PM at UGF,  reduce ringing
• Once PM large enough, no effect
– Taking care of secondary poles and zeros,  reduce
settling time to 1/A0 level
• Pole zero cancellation be accurate and at sufficiently high
frequency
• Cascode or mirror poles sufficiently high frequency
• Reduce parasitic capacitances
– Increasing current
– Using better processes
• Other specifications to improve
– reduced power consumption
– low voltage operation
– low output impedance (to drive resistive load,
or deliver sufficient real power)
– large output swing (large signal to noise ratio)
– large input common mode range
– large CMRR
– large PSRR
– small offset voltage
– improved linearity
– low noise operation
– common mode stability
 Two-Stage Cascode Architecture
• Why Cascode Op Amps?
– Control the frequency behavior
– Increase PSRR
– Simplifies design
• Where is the Cascode Technique Applied?
– First stage -
• Good noise performance
• May require level translation to second stage
• Requires Miller compensation
– Second stage -
• Increases the efficiency of the Miller compensation
• Increases PSRR
– Folded cascode op amp
• Reduce # transistors stacked between Vdd and Vss
 VDD VDD
Differential
Telescopic Vyy
M7 M8
Cascoding
Amplifier Vxx
M5 M6

Vbb
CL M3 M4 CL

M1 M2
Needs CMFB Vin+ Vin-
On either Vyy
Or VG9 M9
Single-ended telescopic cascoding
Analysis very similar to
non-cascoded version:
think of the cascode pair
as a composite transistor.

M2-MC2 has gm=gm2

go=gds2*gdsC2/gmC2

Ao=gm/go
p1=-go/Co
Right half plane zero: gm/Cgd2
 Output swing is much less

Vo1 max: VDD – Vsg3-I1*R + |VTP|

Vo1 min: Vicm – Vgs1 – Vbias – VTN
> Vss + Vdssat5 – Vbias – VTN

Several additional pole-zero pairs

At node D2-SC2:
Pole: g=gmC2+gmbC2+gds2+gdsC2
C=CgsC2+cgd2+cdb2
p=-g/C ≈-gmC2/(CgsC2+cgd2+cdb2)
Zero: z≈-gmC2/CgsC2
Pole-zero cancellation at -2pfT of MC2
 Two stage
M4 M4
bias3
M3 bias2 M3

bias1
M2 M2

Vi1 M1 M1 Vi2

Mb CMFB

Depends on supply and first stage biasing, may

need level shifting
Analysis very similar, except very small go1, more p/z
Cascoding the second stage

Very similar analysis, very small go

Not suitable for low voltage design
 A balanced version

Mirror gain M:
gm6:gm4 =
gm8:gm3 *
gm11:gm10

SR=I6/CL

GB=gm1M/CL Ao = gm1/go * M

Should have small current in these

But parasitic poles should be high enough
 Layout of cascode transistors
With double poly:

In a single poly process:

 Folded cascode
Balanced has better output swing and better
gain than telescopic cascode
Both single stage
Neither require compensation
But balanced limits input common mode
range due to diode connection

folding
 VDDVDD
folded cascode amp
Same GBW as telescopic
3 4
Iss determines slew rate

Vbb
6 5

Vin+ Vin-
1 2 CL
10 11

Iss
8 9

Differential amp requires CMFB

• I1=I2=Iss/2, I3=I4=Iss*1.2~1.5
• Ao=gm1/go; go=gds9*gds11/gm11 +
(gds1+gds3)*gds5/gm5;
• p1=-go/CL; GB = gm1/CL
• Slew rate: Iss/CL
• Vomin = Vg11–VTN, Vomax=Vg5+|VTP|
• Vicmmin = vs+Vgs1,
vicmmax=Vg3+VTN+|VTP|
• Power = (Vdd-Vss)*(I3+I4) + biasing
power
 Appropriate Rz moves zero to cancel p2
VDDVDD Triode VDD
transistor
Vb 3 4 Vb 15

Vx
5
Cc vo+
Vin+ vo1-
Vin-
1 2 Rz
11
Vy CL
Iss 13
9
Vb CMFB

The left side cascode and second stage not shown

 VDDVDD NMOS11b VDD
serves as Rz
Vb 3 4 Vb 15
Triode
vx 5 transistor
Cc
vo1- vo+
Vin+ Vin-
1 2
11a CL
Iss Vy 11b 13
Vb
9
CMFB
 VDD VDD

4 Vb 15

Vbx 5
Cc
vo1- vo+
Vin-
2
11a CL
Iss Vby 11b 13
Vb
9
CMFB
 High speed low voltage design
• Assume VDD-VSS<VTN-VTP, assume a given
Itot
• Use minimum length for high speed operation
• Use appropriate Von13,15 to achieve balance
between high fT and high swing
• Select Von4,5,9,11 so that vo1 has + – 10%
(VDD-VSS) swing
• Set desired vocm at (VDD+VSS+Vdssat13-
Vsdsat15)/2
• Size transistors so that Vgs13 = mid range of
vo1 swing
• Show that the compensation scheme has very
similar pole splitting effect as in 7 transistor op
amp before
• Show that appropriate sizing of M11b can cause
the zero to move over p2
• If CMFB is applied at G3,4, compensation can
be connected to channel of M9
• Show that with an appropriate attenuator, the go
at vo1 can be made zero by positive feedback
from opposite side vo1+ to G5
• Show that with an appropriate gm5, the go at
vo1 can be made zero by positive feedback from
opposite side vD12 to G5
 PUSH-PULL Output Stage

v v

At low frequency, vg7 and vg8 nearly constant as vo swings

 PUSH-PULL Output Stage
• Let AI be the current gain from M1 to M7
• Icc=sCcVg6, (Iss-Icc)/2–>I3, DI7=AI*Icc/2
• KCL at D6: -Icc + Vg6*gm6 +DI7=0, 

Can choose AI so that z cancels p2 for high speed

PUSH-PULL Output Stage
 VDD True push pull
VDD
VDD
3 4

Vin+ Vin-
1 2 CL

Iss
6

Problem: bias current in second stage unknown

 VDD VDD
If VDD-VSS is sufficient
VDD
3 4

5
Vbn
Vbp

CL
Vin+ Vin-
1 2
6
Iss But gain of 1st
stage reduced!
 VDD VDD VDD To recover gain:

VDD
3 4

5
Vbp Vbn

CL
Vin+ Vin-
1 2
6
Iss
 VDD VDD VDD

VDD
3 4

5
Vbp Vbn

CL
Vin+ Vin-
1 2
6
Iss
Figure 7.11 in book: process variations can cause
large change in M21/22 current, and mismatch in
M21 vs M22 bias results in offset voltage
 Figure 7.1-2
Same comment applies to this one

Both can have very small quiescent current when vin≈0

But provide large charging or discharging current
power efficiency
 Dynamically Biased (Switched) Amplifiers
• Switched amplifiers lead to smaller parasitic
capacitors and therefore higher frequency
response.
– Switched amplifiers require a non-overlapping clock
– Switched amplifiers only work during a portion of a
clock period
– Bias conditions are setup on one clock phase and
then maintained by capacitance on the active phase
– Switched amplifiers use switches and capacitors
resulting in feed-through problems
– Simplified circuits on the active phase minimize the
parasitics
 Dynamically Biased Amplifiers
• Two phase non-overlapping clocks
 Dynamically Biased Inverter
In f2 offset and bias
are sampled
In f1, COS provides
offset cancellation plus
bias for M1; CB
provides the bias for
M2.
Dynamic, Push-pull, Cascode Op
Amp
 VDD - VB2 - vIN

vIN - VSS - VB1

 A Dynamic Op Amp which
Operates on Both Clock Phases
True push-pull
Single stage
Differential-in
Single-ended out
No tail current
Off-set cancelled

For large swing:

Remove cascodes

S. Masuda, et. al.,

1984
 LOW VOLTAGE OP AMPS
• We will cover:
– Low voltage input stages
– Low voltage bias circuits
– Low voltage op amps
– Examples
• Methodology:
– Modify standard circuit blocks for reduced
power supply voltage
– Explore new circuits suitable for low voltage
design
ITRS Projection – near term
ITRS Projection – longer term
 Low-Voltage, Strong-Inversion Operation
• Reduced power supply means decreased dynamic range
• Nonlinearity will increase because the transistor is
working close to VDS(sat)
• Large values of λ because the transistor is working close
to VDS(sat)
• Increased drain-bulk and source-bulk capacitances
because they are less reverse biased.
• Large values of currents and W/L ratios to get high
transconductance
• Small values of currents and large values of W/L will give
smallVDS(sat)
• Severely reduced input common mode range
• Switches will require charge pumps
Input common mode range drop

VDD – VDS3sat + VT1 > vicm > VDS5sat + VT1 + VEB1

1.25 -0.25 + 0.75 > vicm > 0.25+0.75+0.25
p-n complementary input pairs

n-channel: vicm > VDSN5sat + VTN1 + VEBN1

p-channel: vicm <VDD- VDSP5sat - VTP1 - VEBP1
Non-constant input gm
constant input gm solution
Set VB1 = Vonn and VB2 = Vonp
Rail-to-rail constant gm input
Rail-to-rail constant gm input

Coban and Allen, 1995

The composite transistor
Bulk-Driven MOSFET
Bulk-Driven, n-channel Differential Amplifier

I1=I2=I5/2
As Vic varies,
Vd5 changes
and gmb varies

Varied gain,
slew rate, gain
bandwidth;
nonlinearity;
and difficulty in
compensation
Bulk-driven current mirrors

Increased vin range and vout range

 Traditional techniques for wide
input and output voltage swings

Io =
Ib Ib Iin+Ib

Iin
VT+2Von 1/4 >2Von
1 1
+
VT+Von
Von – Von
VT+Von
1 1
 Traditional techniques for wide
input and output voltage swings

Iin Io =
Ib Ib Iin
+ VT+2Von Io
Veb
– >2Von
1/4 1
Von Von
VT+Von
1 1
 A 1-Volt, Two-Stage Op Amp

Uses a bulk-driven differential input pair,

wide swing current mirror load, and emitter
follower level shifter
Low voltage VBE and PTAT reference
Low voltage band-gap reference

Needs a low
voltage op amp

Vref=I3*R3=
VGo 1 k A2 VBE  VG 0 m 1 To
R3 [ ( ln( )  ) T  kT  ln( )]
R1 R0 q A1 To R1q T
One example implementation
Threshold Voltage Tuning for low
power supply voltages operation
standard
virtual
transistors
transistors
+
-

V dcn V tn V tn'  Vtn  V dcn

+
-

V dcp V tp V tp'  Vtp  V dcp

Implementation of the voltage
Bias Voltage
sources V dc
-+

f2 f2
f C1 f
IN 1 1 OUT

C2
Bias Voltage V
dc

+ -

f2 f2
f C1 f
IN 1 1 OUT

C2
A low voltage Op Amp core
 Op Amp Implementation
VDD
VDD
R
M3

C
-
+
M2

IN M4
OUT
M1 OUT

M5

VSS

Clock booster Bias voltage generator

Clock booster (doubler)

CB1 >> CBL

 Experimental Results
Power supply 750mV
Slew Rate 3.1V/uS
GB 3.2MHz
DC gain 62dB
Input offset voltage 2.2mV
Input common mode range 0.1V-0.58V
Output swing for linear operation 0.31V-0.58V
PSRR at DC 82dB
CMRR at DC 56dB
Total power consumption 38.3uW
 Regulated Cascode
Vb7 Q8
Q7

VG2
 
Q5  Q6
A4

A3
Vi+ Vi-
VG3
Q1 Q2  
Q3   Q4
A1 A2

Q1 Q2
Vb5
Q11
Regulated Cascode: one
realization
VD

VS
Common mode feedback for low voltage
1.5v op amp for 13bit 60 MHz
ADC
Output Stage and CMFB
Folded cascode with AB output

Lotfi 2002
 Simulated performance
• 0.25 um process
• 1.5 V power supply
• 82 dB DC gain
• 2 V p-p diff output swing
• 170 MHz UGF @ 10 pF load
• 77 PM with b = 1/5
o

• 0.02% 1V step settling time: 8.5 ns

• Full output swing Op Amp power: 25 mW
Differential difference input AB output

Alzaher 2002
Nested Miller Cap Amplifier

Not much successes

Low voltage amp
Low voltage amp
 LOW POWER OP AMPS
• Op Amp Power = (VDD-VSS)*Ibias
– Reduce supply voltage: effect is small
• Many challenges in low voltage design same as
before
– Reduce bias: factor of hundred reduction
• Weak inversion operation
• Nano-amp to small micro-amp currents
• Needs small current biasing circuits and small
current reference generators
• Needs output stage to drive the load
– Design it so that it consume tiny quiescent power
– But generate sufficient current for large signals
– Tradeoff speed for reduced power
 Sub-threshold Operation
Most micro-power op amps use transistors in the
sub-threshold region.

np~1.5; nn~2.5
Two-Stage, Miller Op Amp in Weak Inversion

At VDD-VSS=3V, ID5=0.2uA, ID7=0.5uA, got

A=92dB, GB=50KHz, P=2.1uW
 Push-Pull Output in Weak Inversion
First stage gain

Total gain

S=W/L
 Increasing gain
What is VON?

L5=L12, W12=W5/2
S13<<S4

go

Gain=gm/go
Increasing Iout with positive feedback
When vi1>vi2
i2>i1
i26=i2-i1>0
i27=0
i28=A*i26
itail=i5+i28
=i1+i2
i2/i1=e(vi1-vi2)/nvt
=evin/nvt
i2=i1evin/nvt
i1=I5 /{A+1-(A-1)evin/nvt)}
A=0 is normal case

A > 0 can greatly

enhance available
output current
for load driving
 i1 i1+i2 much faster than i2-i1
as vin 
New i1+i2
i2=i1evin/nvt
i1=i2 A=3
I5

i1+i2=I5 A=2

A=1

A=0

I5 i2