PIPELINED ANALOG TO DIGITAL CONVERTER WITH DIGITAL ASSISTED CALIBRATION

Why Analog to Digital Converters Specifications: Types of ADC : Choice of ADC depends on the architecture, For one-bit per stage pipelined ADC, Component and associated error in a 1-bit
and Digital to Analog Converters? • Frequency • Flash offering the most cost effective Process the input is compared to analog ground pipelined stage
- To convert a real-world signal to a • Resolution • Dual Slope Voltage Temperature(PVT) coordinate for a and the comparator’s output decides if
digital sequence for a digital system to • Power • Successive given resolution.
the residue of that particular stage  Sample and Hold  Charge Injection
process and vice versa • Area Approximation follows 2*Vin + Vref or 2*Vin – Vref.
Eg: Sound-card in PC • ENOB • Pipelined Because of the dependencies seen in the  Comparator  Offset
• Sigma Delta analog octagon, in a few architectures,  GainAmplifier(MX2)  Gain mismatch
Performance Evaluators: though the physical architecture specifies N
• DNL bit resolution, it ends up having the Effective
• INL Number Of Bits (ENOB) less than N.
The analog octagon on the left, relates the • SNR
interdependencies among the design variables, when • SNDR
doing an analog circuit design.
More the resolution or smaller the technology,
For given specification like input range, supply finer is the magnitude of the voltage to be
voltage, frequency of operation, the designer has to resolved, and more will be the relative impact
settle for trade offs among the vertices of the octagon of the non-idealities.
to arrive at a viable solution.

An N- bit ADC has to quantize infinite-valued analog For the design where the MX2 stage gain
Speed and Resolution limitations of the ADC Architectures Impact of the Gain error
signal into many segments so that number of being larger than 2, because of circuit
quantization levels are 2N. Vout = Vin > 0 ? Gain*Vin – Vref : non-ideality, we encounter cases over the
Pipelined ADC is a favourable choice to meet the specifications of 40Msps , resolution of 12 Bits. Gain*Vin – Vref
1LSB = Videal step width = VREF / 2N This architecture provides the necessary trade-offs between speed, accuracy and area and is has an input range where a valid decision cannot
Gain< 2 Gain= 2 Gain> 2 be made due to the output saturation.
Error caused due to quantization cannot be corrected. advantage of using digital error corrections. 1.93 2 2.07
This is considered to be missing
Just like a generic pipelined computer architecture, the input data are converted simultaneously at decisions error, which can’t be mapped
+1.000 1 +1.000 1 +1.000 1
each clock cycle, except for the first input, which takes N clock cycles to get converted, where N is 1 1 1
back to linear scale using any calibration
+0.929 +1.000 +1.140
the resolution of the ADC. -0.859 0 +1.000 1 +1.280 1 technique.
+0.719 1 +1.000 1 +1.280 1
Generic Pipelined ADC Architecture +0.439 1 +1.000 1 +1.560 1 When MX2 stage has a gain < 2, we
-0.120 0 +1.000 1 +2.120 1 encounter few digital logic codes missing
+0.759 1 +1.000 1 +3.240 1 out of the valid 2N levels.
+0.519 1 +1.000 1 +5.480 1
In case of gain < 2, using digital assisted
+0.039 1 +1.000 1 +9.960 1
calibration techniques, we can map the
110110111 111111111 111111111
transfer plot back to a linear scale.
INCORRECT LOGIC
INVALID VOLTAGE

Transfer Plot when MSB stage Gain < 2 : Transfer Plot when MSB stage Gain > 2 :

The graphs above represent output of an ideal(left) and a non-ideal(right) 3 bit ADC for a
ramp input(output ranges from 000 to 111, a total of 8 levels), with the corresponding
quantization error plot beneath. Transfer Plot when MSB stage Gain < 2 :

As seen above, a shift in the transition point of the step due to errors is causing the The plots above show the Transfer plot of a 9 bit ADC when impacted by gain error in
quantization error to change. This can be used as a performance evaluation parameter in the first stage.
terms of static or dc modelling.
The graph on the left is for a case where missing codes exist in the case of gain < 2 and
These discrepancies Differential Non Linearities and Integral Non Linearities where the one on the right shows the missing decisions that exists when gain > 2
DNL = Actual step width – Ideal step width
In the pipelined ADC for N bit resolution, we have K number of stages cascaded, each of the stage At the price of lesser number of digital levels, calibration can be done to map the transfer
A best fit line through the end points of the first and last code transition of the ideal
having a coarse ADC and DAC (N/K). The processed estimate of the signal(output of coarse curve back to a linear scale involving digital assisted calibration techniques. Which
Transfer Function(shown above), with INL being defined as the difference between the
DAC) is subtracted from the input fed to that particular stage, and the error is further resolved by
actual data converter’s code transition points(non ideal curve, shown above). involves tracing the change in effective weight of the digital bit. Karanicolas Algorithm is
the successive stage and the pattern repeats. used for the digital error correction in the implemented model.
The static model of the pipelined ADC is implemented in spyder environment using python