Module 4

PradeepKumar S K
Asst. Professor
Dept. of ECE, KIT, TIPTUR.
E-Mail: pradeepsk13@gmail.com
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CMOS VLSI @ K I T
Boolean Algebra
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PRADEEP S K, Dept Of ECE , KIT , Tiptur
Algebraic Rules
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PRADEEP S K, Dept Of ECE, KIT , Tiptur
Completeness
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Irredundancy:
• A logic expression is irredundant if no literal can
be removed from the expression without changing
its truth value.
• Example: ab+ab’ is redundant, because it can be
reduced to a.
Onset of a function:
The onset is simply the input values for which the
function is true.
Offset of a function:
It is the input values for which the function is false.
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Don’t
cares
F= a’+ab; if we take g= ab; then f= a’+g; We call as factored form

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Field Programmable Gate array
• An FPGA is a device that contains a matrix of reconfigurable gate array

logic circuitry.
• When a FPGA is configured, the internal circuitry is connected in a way
that creates a hardware implementation of the software application.
• Unlike processors, FPGAs use dedicated hardware for processing logic
and do not have an operating system.
• FPGAs are truly parallel in nature so different processing operations do
not have to compete for the same resources. As a result, the performance
of one part of the application is not affected when additional processing
is added.
• Also, multiple control loops can run on a single FPGA device at different
rates. FPGA-based control systems can enforce critical interlock logic
and can be designed to prevent I/O forcing by an operator.
• However, unlike hard-wired printed circuit board (PCB) designs which
have fixed hardware resources, FPGA-based systems can literally rewire
their internal circuitry to allow reconfiguration after the control system
is deployed to the field. FPGA devices deliver the performance and
reliability of dedicated hardware circuitry. 8
Why do we need FPGAs?
• Microprocessors, bus/IO controllers, system timers etc were

implemented using integrated circuit fabrication technology.
Random “glue logic” or interconnects were still required to
help connect the large integrated circuits in order to:
• Generate global control signals (for resets etc.)
• Data signals from one subsystem to another sub system.
• Systems typically consisted of few large scale integrated
components and large number of SSI (small scale integrated
circuit) and MSI (medium scale integrated circuit)
components.Intial attempt to solve this problem led to
development of Custom ICs which were to replace the large
amount of interconnect. This reduced system complexity and
manufacturing cost, and improved performance. However,
custom ICs have their own disadvantages.
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• They are relatively very expensive to develop, and delay introduced
for product to market (time to market) because of increased design
time. There are two kinds of costs involved in development of
custom ICs
• Cost of development and design
• Cost of manufacture
• Therefore the custom IC approach was only viable for products with
very high volume, and which were not time to market sensitive.
FPGAs were introduced as an alternative to custom ICs for
implementing entire system on one chip and to provide flexibility of
reprogramability to the user. Introduction of FPGAs resulted in
improvement of density relative to discrete SSI/MSI components
(within around 10x of custom ICs). Another advantage of FPGAs
over Custom ICs is that with the help of computer aided design
(CAD) tools circuits could be implemented in a short amount of time
(no physical layout process, no mask making, no IC manufacturing)
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Role of FPGA
• There is no wait from completing the design to

obtaining a working chip. The design can he
programmed into the FPGA and tested immediately.
• FPGAs are excellent prototyping vehicles. When the
FPGA is used in the final design. The jump from
prototype to product is much smaller and easier to
negotiate.
• The same FPGA can be used in several different
designs, reducing inventory costs.
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Structure of FPGA
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• In an FPGA logic blocks are implemented using multiple level
low fan-in gates, which gives it a more compact design
compared to an implementation with two-level AND-OR logic.
FPGA provides its user a way to configure:
• The intersection between the logic blocks and
• The function of each logic block.
• Logic block of an FPGA can be configured in such a way that
it can provide functionality as simple as that of transistor or as
complex as that of a microprocessor. It can used to implement
different combinations of combinational and sequential logic
functions. Logic blocks of an FPGA can be implemented by
any of the following:
• 1. Transistor pairs
• 2. combinational gates like basic NAND gates or XOR gates
• 3. n-input Lookup tables
• 4. Multiplexers
• 5. Wide fan-in And-OR structure.
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• Routing in FPGAs consists of wire segments of varying lengths which can be
interconnected via electrically programmable switches. Density of logic block used
in an FPGA depends on length and number of wire segments used for routing.
Number of segments used for interconnection typically is a tradeoff between
density of logic blocks used and amount of area used up for routing. Simplified
version of FPGA internal architecture with routing is shown in Fig
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ASIC vs FPGA
• The Application Specific Integrated Circuit is a unique type of IC that is
designed with a certain purpose in mind. This type of ICs are very
common in most hardware nowadays since building with standard IC
components would lead to big and bulky circuits.
• An ASIC can no longer be altered after it gets out of the production line.
That is why the designers need to be totally sure of their design,
especially when making large quantities of the same ASIC.
• ASICs have a great advantage in terms of recurring costs as very little
material is wasted due to the fixed number of transistors in the design.
• Although the recurring cost of an ASIC is quite low, its non-recurring
cost is relatively high and often reaching into the millions. Since it is non-
recurring though, its value per IC decreases with increased volume.
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• An FPGA (Field Programmable Gate Array) is also a type of IC, but it does
not have the programming built into it during the production. As the name
implies, the IC can be programmed by the user as long as he has the right
tools and proper knowledge.
• The programmable nature of an FPGA allows the manufacturers to correct
mistakes and to even send out patches or updates after the product has been
bought.
• Manufacturers also take advantage of this by creating their prototypes in
an FPGA so that it can be thoroughly tested and revised in the real world
before actually sending out the design to the IC foundry for ASIC
production.
• With an FPGA, a certain number of transistor elements are always wasted
as these packages are standard. This means that the cost of an FPGA is often
higher than that of a comparable ASIC.
• If you analyze the cost of production in relation to the volume, you would
find that as you go lower in production numbers, using FPGA actually
becomes cheaper than using ASICs. 17
Summary
• An ASIC is a unique type of integrated circuit meant for a
specific application while an FPGA is a reprogrammable
integrated circuit.
• An ASIC can no longer be altered once created while an
FPGA can.
• It is common practice to design and test on an FPGA
before implementing on an ASIC.
• An ASIC wastes very little material compared to an
FPGA and the recurring costs are low.
• FPGA is better than an ASIC when building low volume
production circuits.
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FPGA-Based System Design
Goals and Techniques:
• Performance. The logic must run at a required rate. Performance
can be measured in several ways such as throughput and latency.
Clock rate is often used as a measure of performance.
• Power/energy. The chip must often run within an energy or power
budget. Energy consumption is dearly critical in battery-powered
systems. Even if the system is to run off the power grid. heat
dissipation costs money and must be controlled.
• Design time. You can't take forever to design the system FPGAs.
because they are standard pans. have several advantages in design
time. They can be used as prototypes. they can be programmed
quickly. and they can be used as pans in the final design.
• Design Cost: FPGA tools are often less expensive than Custom
VLSI Tool.
• Manufacturing Cost: FPGA’s are generally more expensive than
ASIC.
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Design Challenges
• Multiple levels of abstraction. FPGA design requires
refining an idea through many levels of detail, Starting from
a specification of what the chip must do, the designer must
create an architecture which performs the required function
and then expand the architecture into a logic design.
• Multiple and conflicting costs. Costs may be in dollars such
as the expense of a particular piece of software needed to
design some piece. Costs may also be in performance or
power consumption of the final FPGA.
• Short design time. Electronics markets change extremely
quickly. Getting a chip out faster means reducing your costs
and increasing your revenue. Getting it out late may mean not
making any money at all.
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Hierarchical Design
• Hierarchical design is a standard method for dealing with
complex digital designs.
• It is commonly used in programming: a procedure is
written not as a huge list of primitive statements but as
calls to simpler procedures.
• Each procedure breaks down the task into smaller opera-
tions until each step is refined into a procedure simple
enough to be written directly.
• This technique is commonly known as divide-and-con-
quer-the procedure's complexity is conquered by
recursively breaking it down into manageable pieces.
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Component Types
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Netlist
Component
Version
Version
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FPGA Design Abstraction
• Behavior. A detailed, executable description of what the chip should
do, but not how it should do it.
• Register-transfer. The system's time behavior is fully specified, we
know the allowed input and output values on every clock cycle-but
the logic -isn't specified as gates. The system is specified as Boolean
functions stored in abstract memory elements. Only the vaguest delay
and area estimates can be made from the Boolean logic functions.
• Logic. The system is designed in terms of Boolean logic gates,
latches, and flip-flops. We know a lot about the structure of the
system but still cannot make extremely accurate delay calculations.
• Configuration. The logic must be placed into logic elements around
the FPGA and the proper connections must be made between those
logic elements. Placement and routing perform these important steps.
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• Design abstraction is critical to hardware system design.
Hardware designers use multiple levels of design abstraction to
manage the design process and ensure that they meet major
design goals, such as speed and power consumption.
• Design always requires working down from the top of the
abstraction hierarchy and up from the least abstract description.
• Obviously, work must begin by adding detail to the abstraction -
top-down design adds functional detail.
• Bottom-up analysis and design percolates cost information back
to higher levels of abstraction. Experience will help you judge
costs before you complete the implementation, but most designs
require cycles of top-down design followed by bottom-up
redesign.
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Methodologies
• Complex problems can be tackled using methodologies.
• A methodology provides us with a set of guidelines for what to
do. when to do it, and how to know when we are done.
• Modem digital designers rely on hardware description
languages (HDLs) to describe digital systems.
• Schematics are rarely used to describe logic: block diagrams
are often drawn at higher levels of the system hierarchy but
usually as documentation not as design input.
• HDLs are tied to simulators that understand the semantics of
hardware.
• They are also tied to synthesis tools that generate logic
implementation.
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FPGA Architectures
• In general, FPGAs require three major types of elements:
• These three elements are mixed together to form an
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• Basic structure of an FPGA that incorporates these three elements. The
combinational logic is divided into relatively small units which may be
known as logic elements (LEs) or combinational logic blocks (CLBs).
• The interconnections are made between the logic elements using
programmable interconnect.
• The interconnect may be logically organized into channels or other units.
• FPGAs typically offer several types of interconnect depending on the
distance between the combinational logic blocks that are to be connected;
clock signals are also provided with their own interconnection networks.
• The I/O pins may be referred to as I/O blocks (IOBs). They are generally
programmable to be inputs or outputs and often provide other features
such as low-power or high-speed connections.
• All FPGAs need to be programmed or configured. There are three major
circuit technologies for configuring an FPGA: SRAM, antifuse and Flash.
No matter what circuits are used all the major elements of the FPGA-the
logic.
• The interconnect and the I/O pins-need to be configured. The details of
these elements vary greatly depending on how the FPGA elements are to
be programmed.
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Physical Design for FPGA’s
• Physical design is broken down into two major phases:
• Placement : Determines the positions of the logic elements and I/O pads:
• Routing: Selects the paths for connections between the logic elements
and I/O pads:
• Placement:
• A very important step in physical design cycle.
– A poor placement requires larger area.
– Also results in performance degradation.
• It is the process of arranging a set of modules on the
layout surface.
– Each module has fixed shape and fixed terminal locations.
– A subset of modules may have pre-assigned positions
(e.g., I/O pads).
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The Placement Problem
• Inputs:
– A set of modules with
• well-defined shapes
• fixed locations of pins.
– A netlist.
• Requirements:
– Find locations for each module so

that no two modules overlap.
– The placement is routable.
• Objectives:
– Minimize layout area.
– Reduce the length of critical nets.
– Completion of routing.
– Minimize power dissipation
Chip-level placement
– Normally, floor planning / placement carried out along with pin
assignment.
– Limited number of routing layers (2 to 4).
• Bad placements may be unroutable.
• Can be detected only later (during routing).
• Costly delays in design cycle.
– Minimization of area.
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Classification of Placement Algorithms
Simulated Annealing
Recursive Partitioning
Cluster Growth
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Clustering
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Partitioning
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Routing
• FPGA routing consists of pre-fabricated metal wires
• and programmable switches
• • Interconnect between wire and CLB I/O blocks
• • FPGA routing typically goes through:
• – Routing-resource graph generation
• – Global routing
• – Detailed routing
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PradeepKumar S K

F= a’+ab; if we take g= ab; then f= a’+g; We call as factored form

• An FPGA is a device that contains a matrix of reconfigurable gate array

• Microprocessors, bus/IO controllers, system timers etc were

• There is no wait from completing the design to

• These three elements are mixed together to form an

– Find locations for each module so

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