EDA Introduction: Professor: Sci.D., Prof. Vazgen Melikyan

EDA Introduction
Professor: Sci.D., Prof.

Vazgen Melikyan
Synopsys University Courseware

Copyright © 2017 Synopsys, Inc. All rights reserved.
EDA Introduction
Lecture - 1
1 Developed By: Vazgen Melikyan
Course Overview
 Introduction
 1 lecture
 IC Design Data Formats and Tools
 4 lectures
 Electronic Design Methodology
 4 lectures
 IC Synthesis
 2 lectures
 Databases for EDA
 3 lectures
 IC Design Approaches and Flows
 3 lectures
 EDA Tools
 3 lectures
 Overview of Synopsys EDA Tools
 3 lectures

EDA Introduction
Lecture - 1
Introduction

EDA Introduction
Lecture - 1
IC Design Cycle
Manual
System Chip
Specification
Automation
 Several conflicting considerations:

 Design complexity: large number of devices/transistors
 Performance: optimization requirements for high performance
 Time-to-market: about 15% gain for early customers
 Cost: die area, packaging, testing, etc.
 Others: power, signal integrity (noise, etc.), testability, reliability,
manufacturability, etc.
EDA Introduction
Lecture - 1
IC Design Cycle (2)
 Manual layout design is obviously not practical

 Design complexity:
 Manually drawing layout for a billion transistors would take too long even
if it is known how to:
 Verify (test) designs for functionality, speed, power, etc.
 Complexity scales faster than actual design
 Reuse designs
 Create human-readable designs
 Speed-up design process
 These problems form a great deal of work

 Advancing EDA technology, physical fabrication technology, advanced
designs, and IP form bulk of work (and money) in IC

EDA Introduction
Lecture - 1
IC Design Hierarchy and Abstraction
 Hierarchy shows the structure of a design at different

levels of description.
 Abstraction hides the lower level details.
The use of abstraction makes it possible to reason about
a limited number of interacting parts at each level in the
hierarchy. Each part is itself composed of interacting
subparts at a lower level of abstraction. This
decomposition continues until the basic building blocks
(e.g. transistors) of a IC circuit are reached.

EDA Introduction
Lecture - 1
IC Design Hierarchy
A A Level 1
B D
E F M N
G H O B D Level 2
C
C
I J Level 3
K L E F G HI J M N O
Level 4
K L
b)
a) A
A C
B D I E F I M N
J
C G H K L O
d) e)
c)
 A stylized view of a design (a), its decomposition tree (b), a view of

the design decomposition of entity A at abstraction levels 1 and 2
(c), entity C at levels 2 and 3 (d), the whole design without a
hierarchical organization (e)
EDA Introduction
Lecture - 1
Most Important Entities of IC Design
 Area
One can combine all
 Speed these entities into a
 Power dissipation single cost function - IC
 Design time cost function.
 Testability
It is impossible to try to design an IC circuit at one go
while at the same time optimizing the cost function.
The complexity is simply too high. Two main concepts
that are helpful to deal with this complexity are hierarchy
and abstraction.
EDA Introduction
Lecture - 1
Design Domains
Top-down and bottom-up design methodology
Behavioral Structural
domain domain
High-level synthesis
(algorithmic and system design)
Top-down Logic synthesis

(structural and logic design)
Transistor-level design
Bottom-up Physical design
Physical domain

EDA Introduction
Lecture - 1
Design Domains (2)
Only top-down design methodology
Behavioral Structural
domain domain
High-level synthesis
(algorithmic and system design)
Logic synthesis
(structural and logic design)
Top-down
Transistor layout
Module layout
Cell layout
Floorplans
Physical partitions
Physical domain

EDA Introduction
Lecture - 1
Review of the Design Process
 Application sets specifications and foundries

impose manufacturing constraints
 Design process cycles between synthesis
and verification
Synthesis Verification

EDA Introduction
Lecture - 1
Synthesis
b-view s-view
Architectural Level
…
PC = PC + 1; // increment the Program Counter
FETCH(PC); // fetch next instruction
DECODE(INST); // decode the instruction
…
Logic Level
Technology mapping
Geometrical Level
Physical design
p-view

EDA Introduction
Lecture - 1
Design Process: Synthesis
 Make assumptions and local sub-goals

 For example: transistor saturation
 Select circuit topology
 For example: operational amplifier (single-stage, multi-stage, etc.)
 Formulate analytical equations to guide design
decisions
 For example: bandwidth, gain
 Size devices
 Satisfy performance envelope

EDA Introduction
Lecture - 1
Design Process: Verification
 Simulate circuits (typically Spice or derivatives)

 Validate design across multiple operating environments
 Measure circuit parameters
 Evaluate analytical equations based on simulated values
 Verify assumptions
 For example: check transistors are operating correctly
 Goal: explore limitations of the circuit
 Figure out where and how the circuit breaks

EDA Introduction
Lecture - 1
Design Actions and Tools
 The actions involved to design an IC circuit can be grouped in different

categories according to their types as different types of activities require
different EDA tools.
Synthesis tools
Verification tools
Optimization tools
Design management tools

EDA Introduction
Lecture - 1
Design Description
 Options
 Behavioral
 Parallel algorithm
 Sequential algorithm
 Structural
 Logic family
 Clocking strategy
 Logic structures (complementary, dynamic, transmission gate, etc.)
 Physical domain
 Processing technology
 IC packages
 Cell libraries
EDA Introduction
Lecture - 1
Design Description (2)
 Design Parameters
 Performance (speed, power, function,
flexibility)
 Die size (cost of die)
 Design time
 Testability and ease of testing

EDA Introduction
Lecture - 1
Structured Design Strategy
 Trade-off among design parameters

 Design is a continuous trade-off among design
parameters
 Structured design aims to reduce IC design
complexity and provide teamwork

EDA Introduction
Lecture - 1
Structured Design Strategy (2)
 Structured design techniques

 Hierarchy - reduction of complexity by dividing modules into sub-
modules and then repetition of division until the complexity of
sub-modules is at manageable level.
 Regularity - attempt to divide the hierarchy into a set of similar
building blocks.
 Modularity - well defined interfacing among sub-modules. In
structured domain, interfacing among logic structures; in physical
domain, cell connectivity locations.
 Locality - a form of “information hiding” of a module or sub-
module by specification of interfacing only so that module’s
apparent complexity is reduced.
EDA Introduction
Lecture - 1
Design Options
Design Options
Custom Semicustom
Cell-based Array-based
Standard cells Pre-diffused Pre-wired

Macro cells
Compiled cells (gate arrays) (FPGA's)

EDA Introduction
Lecture - 1
Sample Problems in EDA Industry
 Lack (“insufficient supply”) of qualified engineers

 100s of companies may re-implement same algorithms
 Wasted resources compound the problem of insufficient supply
 Time to market (5-7 year delay from publishing to first

industrial use)
 Academic papers often lack empirics - every user re-runs empirics
 Tool integration (academics tend to focus on isolated optimizations)
 Changes in technology and design processes
 Qualify of Result (QoR)
 Often cannot be evaluated in an isolated (optimization) context
 EDA engineers have no feel for QoR

EDA Introduction
Lecture - 1
IC Design Cycle
System Specification Netlist
Architectural Physical
Design Design
Circuit
Architectural Layout
Specification
Design
or
Fabrication
Functional Logic
Design Synthesis
Chips
Timing and relationship
between functional units Packaging
Logic Packaged and
Design tested chips
RTL in HDL

EDA Introduction
Lecture - 1
History and Evolution of the EDA
 1960. The Hand design
Courtesy TI Courtesy RCA– CMOS Test Courtesy Intel and NY

122 Transistors Pattern Museum of Modern Art
EPROM
Paper designs Cutting Rubylith artwork for mask generation
EDA Introduction
Lecture - 1
History and Evolution of the EDA (2)
 1969. Commercial CAD Gets Started

 Applicon- PCB & IC Digitizing, CAM
 ComputerVision- Wiring, Mapping, Documentation, PCB
 David Mann output for IC masks
 Gerber for PCB artwork
33 MB Disk
 Autotrol for digitizing
Plotter
Mag Tape-Output
Digitizing Keyboard, Tablet Mainframe-500 lbs Photo-Mask

Table/Tablet and CRT 128k; 8-16 bit Generation
EDA Introduction
Lecture - 1
 1970s. Basic Early CAD Applications
Gridded Artwork
Pencil IC/PCB Primitive for
Layouts Database Manufacturing
Schematic Card Deck from Simulation

Keypunch 01110010
00011001
10010110
00011001
01110010
Analog
EDA Introduction
Lecture - 1
 1970s. Automated pattern generation and circuit

simulation
 Digitizing systems (Calma)
 Spice for circuit simulation
 Automatic routing for printed circuit boards (Applicon, CV, Racal-
Redac)
 Captive IC routers (IBM, WE, …)
 GDS II becomes the standard layout format (Calma)
 Schematic capture and logic simulation on workstations (Daisy,
Mentor, Valid)

EDA Introduction
Lecture - 1
 Early 1980s. CAE Environment

VAX780 & Tegas Mentor Mentor
or Valid Simulation Graphics Graphics
Spice, NCA/DRC IDEA IDEA
Domain
Network
DECNET
Daisy Daisy
Schematic Schematic
Capture Capture
Keyboard Keyboard  Schematic Capture

 Interactive Simulation
 Eng’g Doc with graphics
 Fast Schematic Capture
 e-mail
 Remote Fast Simulation  MSpice

EDA Introduction
Lecture - 1
 1980s. Placement & Routing

 Automatic placement & routing
 Design Rule Check (DRC), Layout Versus Schematic
(LVS) comparison
 Verilog and VHDL enable Logic and RTL simulation
 The main players in the commercial arena become
Cadence (Gateway/Tangent/ASI/Valid) and Mentor

EDA Introduction
Lecture - 1
 1980s. ECAD Innovates Netlist from IC Layout –

Enables Layout Versus Schematic (LVS)
G1 Net1
G2
Net1: Net1:
G1-O; G2-I; G1-O; G2-I;
Compare
Error
List
EDA Introduction
Lecture - 1
 1980s. Design Rule Check (DRC)

 Design Rule Check identifies geometry errors in
physical design
Error #1 Error List

Error #1-Enclosure
Error #2 Error #2-Width
Error #3-Spacing
Error #3 Error #4-Spacing
Error #4

EDA Introduction
Lecture - 1
 1980s. HDL Becomes Predominant

process begin sad sad
wait unit sad DAs dd.
CLOCK'stable
and CL a SD sock
if(ENABLE='1') then
Verilog or
TOGGLE<= not
TOGGL sad DAs d d
end if;
end process;
VHDL
CLOCK'stable
and CL a SD sock
if(ENABLE='1') then
TOGGLE<= not
Simulation TOGGL sad
Results Synthesis
Formal
Equivalence G1 Net1
Checking
Simulation G2
Results
Net1:
G1-O; G2-I;

EDA Introduction
Lecture - 1
1990s. Synthesis

CLOCK'stable
and CL a SD sock
if(ENABLE='1') then
Verilog or
TOGGLE<= not
TOGGL sad DAs d d
end if;
end process;
VHDL
CLOCK'stable
and CL a SD sock
if(ENABLE='1') then
TOGGLE<= not
TOGGL sad
Synthesis Schematic Full GDS/LEF
G1 Net1
Technology
Mapping
G2

EDA Introduction
Lecture - 1
 1990s. Synthesis Cell Based Design

process begin
Process wait until not
CLOCK'stable
Design and CLOCK=1;
if(ENABLE='1') then
TOGGLE<= not
RTL / Logic
Rules TOGGLE;
end if;
end process;
Cell Library
EDA Tools
Design

EDA Introduction
Lecture - 1
 1990s. The Netlist Becomes the Center of the

CAD and CAE Universe
Logic Simulation
Netlist
Analog Simulation
IC Place and Route

CAE
PCB Place & Route
Connectivity
CAD
Verification

EDA Introduction
Lecture - 1
 2000. New Design Challenges

 IP
 Timing closure / signal integrity
 Testbenches / assertions
 RET
 DFM / Yield
 Statistical analysis

EDA Introduction
Lecture - 1
Future Trends (1)
Transistors
Lvy Bridge
Oracle SPARC T4
10.000.000.000
Core i7
Dual-Core Intel* Itanium* 2 Processor
Intel* Itanium* Processor
1.000.000.000
Intel* Pentium* 4 Processor
Intel* Pentium* III Processor 100.000.000

Intel* Pentium* II Processor
10.000.000
Intel* Pentium* Processor
Intel486* Processor
1.000.000
Intel386* Processor
286 100.000
8085
8080 10.000
8008
4004
1.000
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020
http://www.cringely.com/2013/10/15/breaking
-moores-law/

EDA Introduction
Lecture - 1
Future Trends (2)
Moore’s Law for contemporary ICs

Exceed Moore’s Law
(multi-crystal chip, system on package, etc.)
1 2 3 4 5 6
Systems with CMOS structures base
Scaling according to Moore’s Law
Interactive systems with non-digital 1. Analog & RF circuits

Integration processing
2. Passive components
130nm of DIPs &
other
(system on package) 3. Powerful components
90nm
types of 4. Sensor components
65nm components 5. Optical components
Digital
45nm information 6. Biochips
Processing
32nm (DIP)
22nm
14nm
7nm

EDA Introduction
Lecture - 1
Future Trends (3)
 IP reuse to increase to over 90% by 2020

 IP based design methodology
 IP diversity matters
 It is kept in check by standards
 Processors, memories and busses define platforms IP
 IP needs to work together – platforms
 IP vendor size matters
 IP needs to be certified by the vendor
 The user certifies the vendor
 Consolidation is unavoidable

EDA Introduction
Lecture - 1
Strong Forces for Consolidation in IP
 Reduce number of IP Vendor 1 IP Vendor 2

vendors to minimize
issues: Application
Specific IP Vendor 3
 Multiple block/vendor Memory USB
Logic
evaluations
 Multiple business models, Basic
Peripherals
contracts, royalties, etc. Time
On-chip USB IP Vendor 4
Serial IO
inter-
 Multiple tools, flows, Memory
Control connect
models, decks, layer etc. “Bus” “PCI” IP Vendor 5

assignments, etc.
 Interoperability IP Vendor 7 IP Vendor 6

EDA Introduction
Lecture - 1
Key Power Management Areas
Low Power Thermal Physics
Management
Application
 Wireless  Microprocessors
 Handheld  Graphics/multimedia  Every design
 Embedded systems  Networking/telecom
Concern
 Battery life  Thermal management  Leakage power

 Lowest leakage  Packaging, cooling  IR-drop
and/or dynamic power cost  Electromigration

EDA Introduction
Lecture - 1
Improving Test Quality
Addressing Defects
 Contact defects require at-speed

delay testing
 Transition and path delay fault
ATPG
 Integration with STA to supply
critical paths
 Metal defects require resistive

shorts testing
 Bridging fault ATPG support
 Extraction integration to identify
most likely bridges based on layout

EDA Introduction
Lecture - 1
Via Reliability - Major Issue
 Manufacturing Problem:
 Formation of voids in vias
caused by thermal stress
 Design Solution:
 Minimization of vias in
routing
 Insertion of redundant vias

EDA Introduction
Lecture - 1
Advanced Silicon Process Rules
 Antenna checking and

repair including diode
insertion
 Metal slotting
 Metal fill
 Via optimization
 Min-area rule
 Fat wire rule with range
specification
Via Optimization Improves Process Yield

EDA Introduction
Lecture - 1
Exploding Verification State Space
Bug
Initial
Capacity Gap
State

EDA Introduction
Lecture - 1
Mixed Simulation and Formal
Verification
Formal Verification
Equivalence
Formal Property Topology Checks Checking
Assertions Coverage
Simulations
Metrics
Properties
Functional
Constraints bugs Code
Feedback
Constrained Random Classes Scenarios
Testbench Infrastructure

EDA Introduction
Lecture - 1
Blocks Getting Bigger and More
Complex
PCI Express
1176JZ-S PCI-X v1.0

1022E
PCI v2.3
PCI v1.1
PCI Cores
922T
USB 2.0 Host
USB 1.1 Host

7TDMI-S
USB 2.0 Device
USB 1.1 Device
ARM Cores USB Cores

EDA Introduction
Lecture - 1
System on Chip (SoC)
CPU Memory
(+DSP) Subsystem
+ cache (SRAM, DRAM, Flash,
SDRAM Controller) Custom
Application-
BlueTooth
DSP
Logic
Specific
Subsystem
Logic
AMBA AHB
AMBA APB
Remap Int. IR I/F UART1 GPIO Timer USB

/Pause Cntrl SATA Enet
UART1 GPIO 2.0

EDA Introduction
Lecture - 1
Layout and Technology
Layout 0.25µ 0.18µ
0.15µ 130nm ≤90nm

EDA Introduction
Lecture - 1
Image Correction
Design
OPC
Mask
Wafer

EDA Introduction
Lecture - 1
Synopsys’ Design and Verification
Continuum Platform
www.synopsys.com

EDA Introduction
Lecture - 1

EDA Introduction: Professor: Sci.D., Prof. Vazgen Melikyan

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EDA Introduction

Professor: Sci.D., Prof.

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

 Several conflicting considerations:

 Manual layout design is obviously not practical

 These problems form a great deal of work

Synopsys University Courseware

 Hierarchy shows the structure of a design at different

Synopsys University Courseware

 A stylized view of a design (a), its decomposition tree (b), a view of

Top-down and bottom-up design methodology

Top-down Logic synthesis

Bottom-up Physical design

Synopsys University Courseware

Synopsys University Courseware

 Application sets specifications and foundries

Synopsys University Courseware

Synopsys University Courseware

 Make assumptions and local sub-goals

Synopsys University Courseware

 Simulate circuits (typically Spice or derivatives)

Synopsys University Courseware

 The actions involved to design an IC circuit can be grouped in different

Design management tools

Synopsys University Courseware

Synopsys University Courseware

 Trade-off among design parameters

Synopsys University Courseware

 Structured design techniques

Standard cells Pre-diffused Pre-wired

Synopsys University Courseware

 Lack (“insufficient supply”) of qualified engineers

 Time to market (5-7 year delay from publishing to first

Synopsys University Courseware

Synopsys University Courseware

 1960. The Hand design

Courtesy TI Courtesy RCA– CMOS Test Courtesy Intel and NY

 1969. Commercial CAD Gets Started

Digitizing Keyboard, Tablet Mainframe-500 lbs Photo-Mask

 1970s. Basic Early CAD Applications

Schematic Card Deck from Simulation

 1970s. Automated pattern generation and circuit

Synopsys University Courseware

 Early 1980s. CAE Environment

Keyboard Keyboard  Schematic Capture

Synopsys University Courseware

 1980s. Placement & Routing

Synopsys University Courseware

 1980s. ECAD Innovates Netlist from IC Layout –

 1980s. Design Rule Check (DRC)

Error #1 Error List

Synopsys University Courseware

 1980s. HDL Becomes Predominant

Synopsys University Courseware

process begin sad sad

Synthesis Schematic Full GDS/LEF

Synopsys University Courseware

 1990s. Synthesis Cell Based Design

Synopsys University Courseware

 1990s. The Netlist Becomes the Center of the

IC Place and Route